diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
| -rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h | 27 |
1 files changed, 22 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h index b1077821..91656156 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h | |||
| @@ -128,14 +128,31 @@ enum { | |||
| 128 | #define PMU_PG_PARAM_CMD_POST_INIT 0x06 | 128 | #define PMU_PG_PARAM_CMD_POST_INIT 0x06 |
| 129 | #define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE 0x07 | 129 | #define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE 0x07 |
| 130 | 130 | ||
| 131 | #define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) | 131 | #define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN (1 << 0) |
| 132 | #define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) | 132 | #define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING (1 << 2) |
| 133 | #define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3) | 133 | #define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3) |
| 134 | #define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING (1 << 5) | ||
| 135 | #define NVGPU_PMU_GR_FEATURE_MASK_UNBIND (1 << 6) | ||
| 136 | #define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE (1 << 7) | ||
| 137 | #define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY (1 << 8) | ||
| 138 | #define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE (1 << 9) | ||
| 139 | #define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM (1 << 10) | ||
| 140 | #define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC (1 << 11) | ||
| 141 | #define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG (1 << 12) | ||
| 134 | 142 | ||
| 135 | #define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3) | ||
| 136 | #define NVGPU_PMU_GR_FEATURE_MASK_ALL \ | 143 | #define NVGPU_PMU_GR_FEATURE_MASK_ALL \ |
| 137 | ( \ | 144 | ( \ |
| 138 | NVGPU_PMU_GR_FEATURE_MASK_RPPG \ | 145 | NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN |\ |
| 146 | NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING |\ | ||
| 147 | NVGPU_PMU_GR_FEATURE_MASK_RPPG |\ | ||
| 148 | NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING |\ | ||
| 149 | NVGPU_PMU_GR_FEATURE_MASK_UNBIND |\ | ||
| 150 | NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE |\ | ||
| 151 | NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY |\ | ||
| 152 | NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE |\ | ||
| 153 | NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM |\ | ||
| 154 | NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC |\ | ||
| 155 | NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG \ | ||
| 139 | ) | 156 | ) |
| 140 | 157 | ||
| 141 | #define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0) | 158 | #define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0) |