diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h | 89 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 5 |
3 files changed, 101 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h index 70184934..90d2d20d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,6 +28,22 @@ | |||
28 | #endif | 28 | #endif |
29 | 29 | ||
30 | /* | 30 | /* |
31 | * READ/WRITE masks for WPR region | ||
32 | */ | ||
33 | /* Readable only from level 2 and 3 client */ | ||
34 | #define LSF_WPR_REGION_RMASK (0xC) | ||
35 | /* Writable only from level 2 and 3 client */ | ||
36 | #define LSF_WPR_REGION_WMASK (0xC) | ||
37 | /* Readable only from level 3 client */ | ||
38 | #define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED (0x8) | ||
39 | /* Writable only from level 3 client */ | ||
40 | #define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED (0x8) | ||
41 | /* Disallow read mis-match for all clients */ | ||
42 | #define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO (0x0) | ||
43 | /* Disallow write mis-match for all clients */ | ||
44 | #define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0) | ||
45 | |||
46 | /* | ||
31 | * Falcon Id Defines | 47 | * Falcon Id Defines |
32 | * Defines a common Light Secure Falcon identifier. | 48 | * Defines a common Light Secure Falcon identifier. |
33 | */ | 49 | */ |
@@ -84,6 +100,42 @@ struct lsf_wpr_header_v1 { | |||
84 | u32 bin_version; | 100 | u32 bin_version; |
85 | u32 status; | 101 | u32 status; |
86 | }; | 102 | }; |
103 | |||
104 | |||
105 | /* | ||
106 | * LSF shared SubWpr Header | ||
107 | * | ||
108 | * use_case_id - Shared SubWpr use case ID (updated by nvgpu) | ||
109 | * start_addr - start address of subWpr (updated by nvgpu) | ||
110 | * size_4K - size of subWpr in 4K (updated by nvgpu) | ||
111 | */ | ||
112 | struct lsf_shared_sub_wpr_header { | ||
113 | u32 use_case_id; | ||
114 | u32 start_addr; | ||
115 | u32 size_4K; | ||
116 | }; | ||
117 | |||
118 | /* shared sub_wpr use case IDs */ | ||
119 | enum { | ||
120 | LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1, | ||
121 | LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2 | ||
122 | }; | ||
123 | |||
124 | #define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX \ | ||
125 | LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA | ||
126 | |||
127 | #define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFF) | ||
128 | |||
129 | #define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES \ | ||
130 | LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX | ||
131 | |||
132 | /* Static sizes of shared subWPRs */ | ||
133 | /* Minimum granularity supported is 4K */ | ||
134 | /* 1MB in 4K */ | ||
135 | #define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100) | ||
136 | /* 4K */ | ||
137 | #define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1) | ||
138 | |||
87 | /* | 139 | /* |
88 | * Bootstrap Owner Defines | 140 | * Bootstrap Owner Defines |
89 | */ | 141 | */ |
@@ -147,13 +199,40 @@ struct lsf_lsb_header_v1 { | |||
147 | /* | 199 | /* |
148 | * Light Secure WPR Content Alignments | 200 | * Light Secure WPR Content Alignments |
149 | */ | 201 | */ |
150 | #define LSF_LSB_HEADER_ALIGNMENT 256 | 202 | #define LSF_WPR_HEADER_ALIGNMENT (256U) |
151 | #define LSF_BL_DATA_ALIGNMENT 256 | 203 | #define LSF_SUB_WPR_HEADER_ALIGNMENT (256U) |
152 | #define LSF_BL_DATA_SIZE_ALIGNMENT 256 | 204 | #define LSF_LSB_HEADER_ALIGNMENT (256U) |
153 | #define LSF_BL_CODE_SIZE_ALIGNMENT 256 | 205 | #define LSF_BL_DATA_ALIGNMENT (256U) |
206 | #define LSF_BL_DATA_SIZE_ALIGNMENT (256U) | ||
207 | #define LSF_BL_CODE_SIZE_ALIGNMENT (256U) | ||
208 | #define LSF_DATA_SIZE_ALIGNMENT (256U) | ||
209 | #define LSF_CODE_SIZE_ALIGNMENT (256U) | ||
210 | |||
211 | /* MMU excepts sub_wpr sizes in units of 4K */ | ||
212 | #define SUB_WPR_SIZE_ALIGNMENT (4096U) | ||
213 | |||
214 | /* | ||
215 | * Maximum WPR Header size | ||
216 | */ | ||
217 | #define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \ | ||
218 | (ALIGN_UP((sizeof(struct lsf_wpr_header_v1) * LSF_FALCON_ID_END), \ | ||
219 | LSF_WPR_HEADER_ALIGNMENT)) | ||
220 | #define LSF_LSB_HEADER_TOTAL_SIZE_MAX (\ | ||
221 | ALIGN_UP(sizeof(struct lsf_lsb_header_v1), LSF_LSB_HEADER_ALIGNMENT)) | ||
222 | |||
223 | /* Maximum SUB WPR header size */ | ||
224 | #define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX (ALIGN_UP( \ | ||
225 | (sizeof(struct lsf_shared_sub_wpr_header) * \ | ||
226 | LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), \ | ||
227 | LSF_SUB_WPR_HEADER_ALIGNMENT)) | ||
228 | |||
154 | 229 | ||
155 | #define LSF_UCODE_DATA_ALIGNMENT 4096 | 230 | #define LSF_UCODE_DATA_ALIGNMENT 4096 |
156 | 231 | ||
232 | /* Defined for 1MB alignment */ | ||
233 | #define SHIFT_1MB (20) | ||
234 | #define SHIFT_4KB (12) | ||
235 | |||
157 | /* | 236 | /* |
158 | * Supporting maximum of 2 regions. | 237 | * Supporting maximum of 2 regions. |
159 | * This is needed to pre-allocate space in DMEM | 238 | * This is needed to pre-allocate space in DMEM |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h index cde8707a..96fb9f19 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -73,12 +73,24 @@ struct ls_flcn_mgr { | |||
73 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ | 73 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ |
74 | }; | 74 | }; |
75 | 75 | ||
76 | /* | ||
77 | * LSFM SUB WPRs struct | ||
78 | * pnext : Next entry in the list, NULL if last | ||
79 | * sub_wpr_header : SubWpr Header struct | ||
80 | */ | ||
81 | struct lsfm_sub_wpr { | ||
82 | struct lsfm_sub_wpr *pnext; | ||
83 | struct lsf_shared_sub_wpr_header sub_wpr_header; | ||
84 | }; | ||
85 | |||
76 | struct ls_flcn_mgr_v1 { | 86 | struct ls_flcn_mgr_v1 { |
77 | u16 managed_flcn_cnt; | 87 | u16 managed_flcn_cnt; |
78 | u32 wpr_size; | 88 | u32 wpr_size; |
79 | u32 disable_mask; | 89 | u32 disable_mask; |
80 | struct lsfm_managed_ucode_img_v2 *ucode_img_list; | 90 | struct lsfm_managed_ucode_img_v2 *ucode_img_list; |
81 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ | 91 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ |
92 | u16 managed_sub_wpr_count; | ||
93 | struct lsfm_sub_wpr *psub_wpr_list; | ||
82 | }; | 94 | }; |
83 | 95 | ||
84 | 96 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index a76db09e..0ffb0488 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -163,10 +163,13 @@ struct gk20a; | |||
163 | /* USERMODE enable bit */ | 163 | /* USERMODE enable bit */ |
164 | #define NVGPU_SUPPORT_USERMODE_SUBMIT 67 | 164 | #define NVGPU_SUPPORT_USERMODE_SUBMIT 67 |
165 | 165 | ||
166 | /* Multiple WPR support */ | ||
167 | #define NVGPU_SUPPORT_MULTIPLE_WPR 68 | ||
168 | |||
166 | /* | 169 | /* |
167 | * Must be greater than the largest bit offset in the above list. | 170 | * Must be greater than the largest bit offset in the above list. |
168 | */ | 171 | */ |
169 | #define NVGPU_MAX_ENABLED_BITS 68 | 172 | #define NVGPU_MAX_ENABLED_BITS 69 |
170 | 173 | ||
171 | /** | 174 | /** |
172 | * nvgpu_is_enabled - Check if the passed flag is enabled. | 175 | * nvgpu_is_enabled - Check if the passed flag is enabled. |