diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 208 |
1 files changed, 208 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index eba6d806..c16d44f1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | |||
@@ -88,6 +88,30 @@ static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) | |||
88 | { | 88 | { |
89 | return 0x800U; | 89 | return 0x800U; |
90 | } | 90 | } |
91 | static inline u32 pwr_falcon_irqstat_ext_ecc_parity_true_f(void) | ||
92 | { | ||
93 | return 0x400U; | ||
94 | } | ||
95 | static inline u32 pwr_pmu_ecc_intr_status_r(void) | ||
96 | { | ||
97 | return 0x0010abfcU; | ||
98 | } | ||
99 | static inline u32 pwr_pmu_ecc_intr_status_corrected_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x1U) << 0U; | ||
102 | } | ||
103 | static inline u32 pwr_pmu_ecc_intr_status_corrected_m(void) | ||
104 | { | ||
105 | return 0x1U << 0U; | ||
106 | } | ||
107 | static inline u32 pwr_pmu_ecc_intr_status_uncorrected_f(u32 v) | ||
108 | { | ||
109 | return (v & 0x1U) << 1U; | ||
110 | } | ||
111 | static inline u32 pwr_pmu_ecc_intr_status_uncorrected_m(void) | ||
112 | { | ||
113 | return 0x1U << 1U; | ||
114 | } | ||
91 | static inline u32 pwr_falcon_irqmode_r(void) | 115 | static inline u32 pwr_falcon_irqmode_r(void) |
92 | { | 116 | { |
93 | return 0x0010a00cU; | 117 | return 0x0010a00cU; |
@@ -160,6 +184,10 @@ static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v) | |||
160 | { | 184 | { |
161 | return (v & 0x1U) << 15U; | 185 | return (v & 0x1U) << 15U; |
162 | } | 186 | } |
187 | static inline u32 pwr_falcon_irqmset_ext_ecc_parity_f(u32 v) | ||
188 | { | ||
189 | return (v & 0x1U) << 10U; | ||
190 | } | ||
163 | static inline u32 pwr_falcon_irqmclr_r(void) | 191 | static inline u32 pwr_falcon_irqmclr_r(void) |
164 | { | 192 | { |
165 | return 0x0010a014U; | 193 | return 0x0010a014U; |
@@ -228,6 +256,10 @@ static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v) | |||
228 | { | 256 | { |
229 | return (v & 0x1U) << 15U; | 257 | return (v & 0x1U) << 15U; |
230 | } | 258 | } |
259 | static inline u32 pwr_falcon_irqmclr_ext_ecc_parity_f(u32 v) | ||
260 | { | ||
261 | return (v & 0x1U) << 10U; | ||
262 | } | ||
231 | static inline u32 pwr_falcon_irqmask_r(void) | 263 | static inline u32 pwr_falcon_irqmask_r(void) |
232 | { | 264 | { |
233 | return 0x0010a018U; | 265 | return 0x0010a018U; |
@@ -300,6 +332,10 @@ static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v) | |||
300 | { | 332 | { |
301 | return (v & 0x1U) << 15U; | 333 | return (v & 0x1U) << 15U; |
302 | } | 334 | } |
335 | static inline u32 pwr_falcon_irqdest_host_ext_ecc_parity_f(u32 v) | ||
336 | { | ||
337 | return (v & 0x1U) << 10U; | ||
338 | } | ||
303 | static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) | 339 | static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) |
304 | { | 340 | { |
305 | return (v & 0x1U) << 16U; | 341 | return (v & 0x1U) << 16U; |
@@ -364,6 +400,10 @@ static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v) | |||
364 | { | 400 | { |
365 | return (v & 0x1U) << 31U; | 401 | return (v & 0x1U) << 31U; |
366 | } | 402 | } |
403 | static inline u32 pwr_falcon_irqdest_target_ext_ecc_parity_f(u32 v) | ||
404 | { | ||
405 | return (v & 0x1U) << 26U; | ||
406 | } | ||
367 | static inline u32 pwr_falcon_curctx_r(void) | 407 | static inline u32 pwr_falcon_curctx_r(void) |
368 | { | 408 | { |
369 | return 0x0010a050U; | 409 | return 0x0010a050U; |
@@ -908,6 +948,174 @@ static inline u32 pwr_pmu_pg_intren_r(u32 i) | |||
908 | { | 948 | { |
909 | return 0x0010a760U + i*4U; | 949 | return 0x0010a760U + i*4U; |
910 | } | 950 | } |
951 | static inline u32 pwr_pmu_falcon_ecc_status_r(void) | ||
952 | { | ||
953 | return 0x0010a6b0U; | ||
954 | } | ||
955 | static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_imem_f(u32 v) | ||
956 | { | ||
957 | return (v & 0x1U) << 0U; | ||
958 | } | ||
959 | static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_imem_m(void) | ||
960 | { | ||
961 | return 0x1U << 0U; | ||
962 | } | ||
963 | static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_dmem_f(u32 v) | ||
964 | { | ||
965 | return (v & 0x1U) << 1U; | ||
966 | } | ||
967 | static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_dmem_m(void) | ||
968 | { | ||
969 | return 0x1U << 1U; | ||
970 | } | ||
971 | static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_imem_f(u32 v) | ||
972 | { | ||
973 | return (v & 0x1U) << 8U; | ||
974 | } | ||
975 | static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m(void) | ||
976 | { | ||
977 | return 0x1U << 8U; | ||
978 | } | ||
979 | static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) | ||
980 | { | ||
981 | return (v & 0x1U) << 9U; | ||
982 | } | ||
983 | static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_m(void) | ||
984 | { | ||
985 | return 0x1U << 9U; | ||
986 | } | ||
987 | static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) | ||
988 | { | ||
989 | return (v & 0x1U) << 16U; | ||
990 | } | ||
991 | static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) | ||
992 | { | ||
993 | return 0x1U << 16U; | ||
994 | } | ||
995 | static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) | ||
996 | { | ||
997 | return (v & 0x1U) << 18U; | ||
998 | } | ||
999 | static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) | ||
1000 | { | ||
1001 | return 0x1U << 18U; | ||
1002 | } | ||
1003 | static inline u32 pwr_pmu_falcon_ecc_status_reset_f(u32 v) | ||
1004 | { | ||
1005 | return (v & 0x1U) << 31U; | ||
1006 | } | ||
1007 | static inline u32 pwr_pmu_falcon_ecc_status_reset_task_f(void) | ||
1008 | { | ||
1009 | return 0x80000000U; | ||
1010 | } | ||
1011 | static inline u32 pwr_pmu_falcon_ecc_address_r(void) | ||
1012 | { | ||
1013 | return 0x0010a6b4U; | ||
1014 | } | ||
1015 | static inline u32 pwr_pmu_falcon_ecc_address_index_f(u32 v) | ||
1016 | { | ||
1017 | return (v & 0xffffffU) << 0U; | ||
1018 | } | ||
1019 | static inline u32 pwr_pmu_falcon_ecc_address_type_f(u32 v) | ||
1020 | { | ||
1021 | return (v & 0xfU) << 20U; | ||
1022 | } | ||
1023 | static inline u32 pwr_pmu_falcon_ecc_address_type_imem_f(void) | ||
1024 | { | ||
1025 | return 0x0U; | ||
1026 | } | ||
1027 | static inline u32 pwr_pmu_falcon_ecc_address_type_dmem_f(void) | ||
1028 | { | ||
1029 | return 0x100000U; | ||
1030 | } | ||
1031 | static inline u32 pwr_pmu_falcon_ecc_address_row_address_s(void) | ||
1032 | { | ||
1033 | return 16U; | ||
1034 | } | ||
1035 | static inline u32 pwr_pmu_falcon_ecc_address_row_address_f(u32 v) | ||
1036 | { | ||
1037 | return (v & 0xffffU) << 0U; | ||
1038 | } | ||
1039 | static inline u32 pwr_pmu_falcon_ecc_address_row_address_m(void) | ||
1040 | { | ||
1041 | return 0xffffU << 0U; | ||
1042 | } | ||
1043 | static inline u32 pwr_pmu_falcon_ecc_address_row_address_v(u32 r) | ||
1044 | { | ||
1045 | return (r >> 0U) & 0xffffU; | ||
1046 | } | ||
1047 | static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_r(void) | ||
1048 | { | ||
1049 | return 0x0010a6b8U; | ||
1050 | } | ||
1051 | static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_s(void) | ||
1052 | { | ||
1053 | return 16U; | ||
1054 | } | ||
1055 | static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_f(u32 v) | ||
1056 | { | ||
1057 | return (v & 0xffffU) << 0U; | ||
1058 | } | ||
1059 | static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_m(void) | ||
1060 | { | ||
1061 | return 0xffffU << 0U; | ||
1062 | } | ||
1063 | static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_v(u32 r) | ||
1064 | { | ||
1065 | return (r >> 0U) & 0xffffU; | ||
1066 | } | ||
1067 | static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_s(void) | ||
1068 | { | ||
1069 | return 16U; | ||
1070 | } | ||
1071 | static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_f(u32 v) | ||
1072 | { | ||
1073 | return (v & 0xffffU) << 16U; | ||
1074 | } | ||
1075 | static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_m(void) | ||
1076 | { | ||
1077 | return 0xffffU << 16U; | ||
1078 | } | ||
1079 | static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_v(u32 r) | ||
1080 | { | ||
1081 | return (r >> 16U) & 0xffffU; | ||
1082 | } | ||
1083 | static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_r(void) | ||
1084 | { | ||
1085 | return 0x0010a6bcU; | ||
1086 | } | ||
1087 | static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_s(void) | ||
1088 | { | ||
1089 | return 16U; | ||
1090 | } | ||
1091 | static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_f(u32 v) | ||
1092 | { | ||
1093 | return (v & 0xffffU) << 0U; | ||
1094 | } | ||
1095 | static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_m(void) | ||
1096 | { | ||
1097 | return 0xffffU << 0U; | ||
1098 | } | ||
1099 | static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_v(u32 r) | ||
1100 | { | ||
1101 | return (r >> 0U) & 0xffffU; | ||
1102 | } | ||
1103 | static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_s(void) | ||
1104 | { | ||
1105 | return 16U; | ||
1106 | } | ||
1107 | static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) | ||
1108 | { | ||
1109 | return (v & 0xffffU) << 16U; | ||
1110 | } | ||
1111 | static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_m(void) | ||
1112 | { | ||
1113 | return 0xffffU << 16U; | ||
1114 | } | ||
1115 | static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) | ||
1116 | { | ||
1117 | return (r >> 16U) & 0xffffU; | ||
1118 | } | ||
911 | static inline u32 pwr_fbif_transcfg_r(u32 i) | 1119 | static inline u32 pwr_fbif_transcfg_r(u32 i) |
912 | { | 1120 | { |
913 | return 0x0010ae00U + i*4U; | 1121 | return 0x0010ae00U + i*4U; |