diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/channel.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/channel_sync.h | 113 |
2 files changed, 116 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h index 6cca843e..cd4fadf8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/channel.h +++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h | |||
@@ -35,7 +35,7 @@ struct gk20a; | |||
35 | struct dbg_session_gk20a; | 35 | struct dbg_session_gk20a; |
36 | struct gk20a_fence; | 36 | struct gk20a_fence; |
37 | struct fifo_profile_gk20a; | 37 | struct fifo_profile_gk20a; |
38 | struct gk20a_channel_sync; | 38 | struct nvgpu_channel_sync; |
39 | struct nvgpu_gpfifo_userdata; | 39 | struct nvgpu_gpfifo_userdata; |
40 | 40 | ||
41 | /* Flags to be passed to gk20a_channel_alloc_gpfifo() */ | 41 | /* Flags to be passed to gk20a_channel_alloc_gpfifo() */ |
@@ -289,8 +289,8 @@ struct channel_gk20a { | |||
289 | struct nvgpu_list_node dbg_s_list; | 289 | struct nvgpu_list_node dbg_s_list; |
290 | 290 | ||
291 | struct nvgpu_mutex sync_lock; | 291 | struct nvgpu_mutex sync_lock; |
292 | struct gk20a_channel_sync *sync; | 292 | struct nvgpu_channel_sync *sync; |
293 | struct gk20a_channel_sync *user_sync; | 293 | struct nvgpu_channel_sync *user_sync; |
294 | 294 | ||
295 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | 295 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION |
296 | u64 virt_ctx; | 296 | u64 virt_ctx; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h b/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h new file mode 100644 index 00000000..b5936edc --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h | |||
@@ -0,0 +1,113 @@ | |||
1 | /* | ||
2 | * | ||
3 | * Nvgpu Channel Synchronization Abstraction | ||
4 | * | ||
5 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
6 | * | ||
7 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
8 | * copy of this software and associated documentation files (the "Software"), | ||
9 | * to deal in the Software without restriction, including without limitation | ||
10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
11 | * and/or sell copies of the Software, and to permit persons to whom the | ||
12 | * Software is furnished to do so, subject to the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice shall be included in | ||
15 | * all copies or substantial portions of the Software. | ||
16 | * | ||
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
23 | * DEALINGS IN THE SOFTWARE. | ||
24 | */ | ||
25 | |||
26 | #ifndef NVGPU_CHANNEL_SYNC_H | ||
27 | #define NVGPU_CHANNEL_SYNC_H | ||
28 | |||
29 | #include <nvgpu/atomic.h> | ||
30 | |||
31 | struct nvgpu_channel_sync; | ||
32 | struct priv_cmd_entry; | ||
33 | struct channel_gk20a; | ||
34 | struct gk20a_fence; | ||
35 | struct gk20a; | ||
36 | struct nvgpu_semaphore; | ||
37 | |||
38 | struct nvgpu_channel_sync { | ||
39 | nvgpu_atomic_t refcount; | ||
40 | |||
41 | /* Generate a gpu wait cmdbuf from syncpoint. | ||
42 | * Returns a gpu cmdbuf that performs the wait when executed | ||
43 | */ | ||
44 | int (*wait_syncpt)(struct nvgpu_channel_sync *s, u32 id, u32 thresh, | ||
45 | struct priv_cmd_entry *entry); | ||
46 | |||
47 | /* Generate a gpu wait cmdbuf from sync fd. | ||
48 | * Returns a gpu cmdbuf that performs the wait when executed | ||
49 | */ | ||
50 | int (*wait_fd)(struct nvgpu_channel_sync *s, int fd, | ||
51 | struct priv_cmd_entry *entry, int max_wait_cmds); | ||
52 | |||
53 | /* Increment syncpoint/semaphore. | ||
54 | * Returns | ||
55 | * - a gpu cmdbuf that performs the increment when executed, | ||
56 | * - a fence that can be passed to wait_cpu() and is_expired(). | ||
57 | */ | ||
58 | int (*incr)(struct nvgpu_channel_sync *s, | ||
59 | struct priv_cmd_entry *entry, | ||
60 | struct gk20a_fence *fence, | ||
61 | bool need_sync_fence, | ||
62 | bool register_irq); | ||
63 | |||
64 | /* Increment syncpoint/semaphore, so that the returned fence represents | ||
65 | * work completion (may need wfi) and can be returned to user space. | ||
66 | * Returns | ||
67 | * - a gpu cmdbuf that performs the increment when executed, | ||
68 | * - a fence that can be passed to wait_cpu() and is_expired(), | ||
69 | * - a gk20a_fence that signals when the incr has happened. | ||
70 | */ | ||
71 | int (*incr_user)(struct nvgpu_channel_sync *s, | ||
72 | int wait_fence_fd, | ||
73 | struct priv_cmd_entry *entry, | ||
74 | struct gk20a_fence *fence, | ||
75 | bool wfi, | ||
76 | bool need_sync_fence, | ||
77 | bool register_irq); | ||
78 | |||
79 | /* Reset the channel syncpoint/semaphore. */ | ||
80 | void (*set_min_eq_max)(struct nvgpu_channel_sync *s); | ||
81 | |||
82 | /* | ||
83 | * Set the channel syncpoint/semaphore to safe state | ||
84 | * This should be used to reset User managed syncpoint since we don't | ||
85 | * track threshold values for those syncpoints | ||
86 | */ | ||
87 | void (*set_safe_state)(struct nvgpu_channel_sync *s); | ||
88 | |||
89 | /* Returns the sync point id or negative number if no syncpt*/ | ||
90 | int (*syncpt_id)(struct nvgpu_channel_sync *s); | ||
91 | |||
92 | /* Returns the sync point address of sync point or 0 if not supported */ | ||
93 | u64 (*syncpt_address)(struct nvgpu_channel_sync *s); | ||
94 | |||
95 | /* Free the resources allocated by nvgpu_channel_sync_create. */ | ||
96 | void (*destroy)(struct nvgpu_channel_sync *s); | ||
97 | }; | ||
98 | |||
99 | void channel_sync_semaphore_gen_wait_cmd(struct channel_gk20a *c, | ||
100 | struct nvgpu_semaphore *sema, struct priv_cmd_entry *wait_cmd, | ||
101 | u32 wait_cmd_size, int pos); | ||
102 | |||
103 | int channel_sync_syncpt_gen_wait_cmd(struct channel_gk20a *c, | ||
104 | u32 id, u32 thresh, struct priv_cmd_entry *wait_cmd, | ||
105 | u32 wait_cmd_size, int pos, bool preallocated); | ||
106 | |||
107 | void nvgpu_channel_sync_destroy(struct nvgpu_channel_sync *sync, | ||
108 | bool set_safe_state); | ||
109 | struct nvgpu_channel_sync *nvgpu_channel_sync_create(struct channel_gk20a *c, | ||
110 | bool user_managed); | ||
111 | bool nvgpu_channel_sync_needs_os_fence_framework(struct gk20a *g); | ||
112 | |||
113 | #endif /* NVGPU_GK20A_CHANNEL_SYNC_GK20A_H */ | ||