diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | 53 |
1 files changed, 39 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h index 2ea0c548..81a1d72e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -31,16 +31,34 @@ | |||
31 | #include "gpmuifvolt.h" | 31 | #include "gpmuifvolt.h" |
32 | #include <nvgpu/flcnif_cmn.h> | 32 | #include <nvgpu/flcnif_cmn.h> |
33 | 33 | ||
34 | |||
35 | /* | ||
36 | * Try to get gpc2clk, mclk, sys2clk, xbar2clk work for Pascal | ||
37 | * | ||
38 | * mclk is same for both | ||
39 | * gpc2clk is 17 for Pascal and 13 for Volta, making it 17 | ||
40 | * as volta uses gpcclk | ||
41 | * sys2clk is 20 in Pascal and 15 in Volta. | ||
42 | * Changing for Pascal would break nvdclk of Volta | ||
43 | * xbar2clk is 19 in Pascal and 14 in Volta | ||
44 | * Changing for Pascal would break pwrclk of Volta | ||
45 | */ | ||
34 | enum nv_pmu_clk_clkwhich { | 46 | enum nv_pmu_clk_clkwhich { |
35 | clkwhich_mclk = 5, | 47 | clkwhich_gpcclk = 1, |
36 | clkwhich_dispclk = 7, | 48 | clkwhich_xbarclk = 2, |
37 | clkwhich_gpc2clk = 17, | 49 | clkwhich_sysclk = 3, |
38 | clkwhich_xbar2clk = 19, | 50 | clkwhich_hubclk = 4, |
39 | clkwhich_sys2clk = 20, | 51 | clkwhich_mclk = 5, |
40 | clkwhich_hub2clk = 21, | 52 | clkwhich_hostclk = 6, |
41 | clkwhich_pwrclk = 24, | 53 | clkwhich_dispclk = 7, |
42 | clkwhich_nvdclk = 25, | 54 | clkwhich_xclk = 12, |
43 | clkwhich_pciegenclk = 31, | 55 | clkwhich_gpc2clk = 17, |
56 | clkwhich_xbar2clk = 14, | ||
57 | clkwhich_sys2clk = 15, | ||
58 | clkwhich_hub2clk = 16, | ||
59 | clkwhich_pwrclk = 19, | ||
60 | clkwhich_nvdclk = 20, | ||
61 | clkwhich_pciegenclk = 26, | ||
44 | }; | 62 | }; |
45 | 63 | ||
46 | /* | 64 | /* |
@@ -62,8 +80,10 @@ enum nv_pmu_clk_clkwhich { | |||
62 | struct nv_pmu_clk_clk_domain_boardobjgrp_set_header { | 80 | struct nv_pmu_clk_clk_domain_boardobjgrp_set_header { |
63 | struct nv_pmu_boardobjgrp_e32 super; | 81 | struct nv_pmu_boardobjgrp_e32 super; |
64 | u32 vbios_domains; | 82 | u32 vbios_domains; |
83 | struct ctrl_boardobjgrp_mask_e32 prog_domains_mask; | ||
65 | struct ctrl_boardobjgrp_mask_e32 master_domains_mask; | 84 | struct ctrl_boardobjgrp_mask_e32 master_domains_mask; |
66 | u16 cntr_sampling_periodms; | 85 | u16 cntr_sampling_periodms; |
86 | u8 version; | ||
67 | bool b_override_o_v_o_c; | 87 | bool b_override_o_v_o_c; |
68 | bool b_debug_mode; | 88 | bool b_debug_mode; |
69 | bool b_enforce_vf_monotonicity; | 89 | bool b_enforce_vf_monotonicity; |
@@ -93,22 +113,24 @@ struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set { | |||
93 | struct nv_pmu_clk_clk_domain_3x_boardobj_set super; | 113 | struct nv_pmu_clk_clk_domain_3x_boardobj_set super; |
94 | u8 clk_prog_idx_first; | 114 | u8 clk_prog_idx_first; |
95 | u8 clk_prog_idx_last; | 115 | u8 clk_prog_idx_last; |
96 | u8 noise_unaware_ordering_index; | ||
97 | u8 noise_aware_ordering_index; | ||
98 | bool b_force_noise_unaware_ordering; | 116 | bool b_force_noise_unaware_ordering; |
99 | int factory_offset_khz; | 117 | struct ctrl_clk_freq_delta factory_delta; |
100 | short freq_delta_min_mhz; | 118 | short freq_delta_min_mhz; |
101 | short freq_delta_max_mhz; | 119 | short freq_delta_max_mhz; |
102 | struct ctrl_clk_clk_delta deltas; | 120 | struct ctrl_clk_clk_delta deltas; |
121 | u8 noise_unaware_ordering_index; | ||
122 | u8 noise_aware_ordering_index; | ||
103 | }; | 123 | }; |
104 | 124 | ||
105 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { | 125 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { |
106 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | 126 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; |
127 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
107 | u32 slave_idxs_mask; | 128 | u32 slave_idxs_mask; |
108 | }; | 129 | }; |
109 | 130 | ||
110 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { | 131 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { |
111 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | 132 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; |
133 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
112 | u8 master_idx; | 134 | u8 master_idx; |
113 | }; | 135 | }; |
114 | 136 | ||
@@ -143,21 +165,24 @@ struct nv_pmu_clk_clk_prog_1x_boardobj_set { | |||
143 | 165 | ||
144 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set { | 166 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set { |
145 | struct nv_pmu_clk_clk_prog_1x_boardobj_set super; | 167 | struct nv_pmu_clk_clk_prog_1x_boardobj_set super; |
168 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
146 | bool b_o_c_o_v_enabled; | 169 | bool b_o_c_o_v_enabled; |
147 | struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[ | 170 | struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[ |
148 | CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES]; | 171 | CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES]; |
149 | union ctrl_clk_clk_prog_1x_master_source_data source_data; | ||
150 | struct ctrl_clk_clk_delta deltas; | 172 | struct ctrl_clk_clk_delta deltas; |
173 | union ctrl_clk_clk_prog_1x_master_source_data source_data; | ||
151 | }; | 174 | }; |
152 | 175 | ||
153 | struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set { | 176 | struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set { |
154 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; | 177 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; |
178 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
155 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[ | 179 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[ |
156 | CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; | 180 | CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; |
157 | }; | 181 | }; |
158 | 182 | ||
159 | struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set { | 183 | struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set { |
160 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; | 184 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; |
185 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
161 | struct ctrl_clk_clk_prog_1x_master_table_slave_entry | 186 | struct ctrl_clk_clk_prog_1x_master_table_slave_entry |
162 | slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; | 187 | slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; |
163 | }; | 188 | }; |