diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/bios.h | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | 10 |
2 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 75f8da35..86e009a3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h | |||
@@ -813,12 +813,15 @@ struct vbios_voltage_policy_table_1x_entry { | |||
813 | u8 type; | 813 | u8 type; |
814 | u32 param0; | 814 | u32 param0; |
815 | u32 param1; | 815 | u32 param1; |
816 | u32 param2; | ||
817 | u32 param3; | ||
816 | } __packed; | 818 | } __packed; |
817 | 819 | ||
818 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00 | 820 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00 |
819 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01 | 821 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01 |
820 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02 | 822 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02 |
821 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03 | 823 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03 |
824 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04 | ||
822 | 825 | ||
823 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ | 826 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ |
824 | GENMASK(7, 0) | 827 | GENMASK(7, 0) |
@@ -839,6 +842,16 @@ struct vbios_voltage_policy_table_1x_entry { | |||
839 | GENMASK(31, 24) | 842 | GENMASK(31, 24) |
840 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24 | 843 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24 |
841 | 844 | ||
845 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ | ||
846 | GENMASK(15, 0) | ||
847 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT 0 | ||
848 | #define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_MASK \ | ||
849 | GENMASK(31, 0) | ||
850 | #define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_SHIFT 0 | ||
851 | #define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_MASK \ | ||
852 | GENMASK(31, 0) | ||
853 | #define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_SHIFT 0 | ||
854 | |||
842 | /* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */ | 855 | /* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */ |
843 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ | 856 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ |
844 | GENMASK(15, 0) | 857 | GENMASK(15, 0) |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h index 3b286139..313a3b2a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | |||
@@ -104,6 +104,7 @@ NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device); | |||
104 | /* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ | 104 | /* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ |
105 | struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { | 105 | struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { |
106 | struct nv_pmu_boardobjgrp_e32 super; | 106 | struct nv_pmu_boardobjgrp_e32 super; |
107 | u8 perf_core_vf_seq_policy_idx; | ||
107 | }; | 108 | }; |
108 | 109 | ||
109 | struct nv_pmu_volt_volt_policy_boardobj_set { | 110 | struct nv_pmu_volt_volt_policy_boardobj_set { |
@@ -114,6 +115,13 @@ struct nv_pmu_volt_volt_policy_sr_boardobj_set { | |||
114 | u8 rail_idx; | 115 | u8 rail_idx; |
115 | }; | 116 | }; |
116 | 117 | ||
118 | struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set { | ||
119 | struct nv_pmu_volt_volt_policy_sr_boardobj_set super; | ||
120 | u16 inter_switch_delay_us; | ||
121 | u32 ramp_up_step_size_uv; | ||
122 | u32 ramp_down_step_size_uv; | ||
123 | }; | ||
124 | |||
117 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set { | 125 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set { |
118 | struct nv_pmu_volt_volt_policy_boardobj_set super; | 126 | struct nv_pmu_volt_volt_policy_boardobj_set super; |
119 | u8 rail_idx_master; | 127 | u8 rail_idx_master; |
@@ -138,6 +146,8 @@ union nv_pmu_volt_volt_policy_boardobj_set_union { | |||
138 | struct nv_pmu_boardobj board_obj; | 146 | struct nv_pmu_boardobj board_obj; |
139 | struct nv_pmu_volt_volt_policy_boardobj_set super; | 147 | struct nv_pmu_volt_volt_policy_boardobj_set super; |
140 | struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail; | 148 | struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail; |
149 | struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set | ||
150 | single_rail_ms; | ||
141 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail; | 151 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail; |
142 | struct nv_pmu_volt_volt_policy_srms_boardobj_set | 152 | struct nv_pmu_volt_volt_policy_srms_boardobj_set |
143 | split_rail_m_s; | 153 | split_rail_m_s; |