diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include/nvgpu/semaphore.h')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/semaphore.h | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h index d36a3270..a4af1ca3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h +++ b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -58,17 +58,8 @@ struct nvgpu_semaphore_int { | |||
58 | int idx; /* Semaphore index. */ | 58 | int idx; /* Semaphore index. */ |
59 | u32 offset; /* Offset into the pool. */ | 59 | u32 offset; /* Offset into the pool. */ |
60 | nvgpu_atomic_t next_value; /* Next available value. */ | 60 | nvgpu_atomic_t next_value; /* Next available value. */ |
61 | u32 nr_incrs; /* Number of increments programmed. */ | ||
62 | struct nvgpu_semaphore_pool *p; /* Pool that owns this sema. */ | 61 | struct nvgpu_semaphore_pool *p; /* Pool that owns this sema. */ |
63 | struct channel_gk20a *ch; /* Channel that owns this sema. */ | 62 | struct channel_gk20a *ch; /* Channel that owns this sema. */ |
64 | struct nvgpu_list_node hw_sema_list; /* List of HW semaphores. */ | ||
65 | }; | ||
66 | |||
67 | static inline struct nvgpu_semaphore_int * | ||
68 | nvgpu_semaphore_int_from_hw_sema_list(struct nvgpu_list_node *node) | ||
69 | { | ||
70 | return (struct nvgpu_semaphore_int *) | ||
71 | ((uintptr_t)node - offsetof(struct nvgpu_semaphore_int, hw_sema_list)); | ||
72 | }; | 63 | }; |
73 | 64 | ||
74 | /* | 65 | /* |
@@ -94,7 +85,6 @@ struct nvgpu_semaphore_pool { | |||
94 | u64 gpu_va_ro; /* GPU access to the pool. */ | 85 | u64 gpu_va_ro; /* GPU access to the pool. */ |
95 | int page_idx; /* Index into sea bitmap. */ | 86 | int page_idx; /* Index into sea bitmap. */ |
96 | 87 | ||
97 | struct nvgpu_list_node hw_semas; /* List of HW semas. */ | ||
98 | DECLARE_BITMAP(semas_alloced, PAGE_SIZE / SEMAPHORE_SIZE); | 88 | DECLARE_BITMAP(semas_alloced, PAGE_SIZE / SEMAPHORE_SIZE); |
99 | 89 | ||
100 | struct nvgpu_semaphore_sea *sema_sea; /* Sea that owns this pool. */ | 90 | struct nvgpu_semaphore_sea *sema_sea; /* Sea that owns this pool. */ |