1 files changed, 24 insertions, 24 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
index 1ba9963c..c156a6c0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
@@ -28,9 +28,9 @@
 /*PG defines*/
 
 /* Identifier for each PG */
-#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000)
-#define PMU_PG_ELPG_ENGINE_ID_MS       (0x00000004)
-#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005)
+#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS          (0x00000000U)
+#define PMU_PG_ELPG_ENGINE_ID_MS                (0x00000004U)
+#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE    (0x00000005U)
 #define PMU_PG_ELPG_ENGINE_MAX    PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
 
 /* PG message */
@@ -173,23 +173,23 @@ enum {
         SLOWDOWN_FACTOR_FPDIV_BYMAX,
 };
 
-#define PMU_PG_PARAM_CMD_GR_INIT_PARAM  0x0
-#define PMU_PG_PARAM_CMD_MS_INIT_PARAM  0x01
-#define PMU_PG_PARAM_CMD_MCLK_CHANGE  0x04
-#define PMU_PG_PARAM_CMD_POST_INIT  0x06
-#define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE  0x07
-
-#define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN     (1 << 0)
-#define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING      (1 << 2)
-#define NVGPU_PMU_GR_FEATURE_MASK_RPPG              (1 << 3)
-#define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING         (1 << 5)
-#define NVGPU_PMU_GR_FEATURE_MASK_UNBIND            (1 << 6)
-#define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE (1 << 7)
-#define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY       (1 << 8)
-#define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE       (1 << 9)
-#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM         (1 << 10)
-#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC        (1 << 11)
-#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG       (1 << 12)
+#define PMU_PG_PARAM_CMD_GR_INIT_PARAM                  0x0U
+#define PMU_PG_PARAM_CMD_MS_INIT_PARAM                  0x01U
+#define PMU_PG_PARAM_CMD_MCLK_CHANGE                    0x04U
+#define PMU_PG_PARAM_CMD_POST_INIT                      0x06U
+#define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE        0x07U
+
+#define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN     BIT32(0)
+#define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING      BIT32(2)
+#define NVGPU_PMU_GR_FEATURE_MASK_RPPG              BIT32(3)
+#define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING         BIT32(5)
+#define NVGPU_PMU_GR_FEATURE_MASK_UNBIND            BIT32(6)
+#define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE BIT32(7)
+#define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY       BIT32(8)
+#define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE       BIT32(9)
+#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM         BIT32(10)
+#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC        BIT32(11)
+#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG       BIT32(12)
 
 #define NVGPU_PMU_GR_FEATURE_MASK_ALL   \
         (       \
@@ -206,10 +206,10 @@ enum {
                 NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG           \
         )
 
-#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING  (1 << 0)
-#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR        (1 << 1)
-#define NVGPU_PMU_MS_FEATURE_MASK_RPPG          (1 << 8)
-#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING   (1 << 5)
+#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING  BIT32(0)
+#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR        BIT32(1)
+#define NVGPU_PMU_MS_FEATURE_MASK_RPPG          BIT32(8)
+#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING   BIT32(5)
 
 #define NVGPU_PMU_MS_FEATURE_MASK_ALL   \
         (       \