summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h')
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h187
1 files changed, 187 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
new file mode 100644
index 00000000..f8c15324
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
@@ -0,0 +1,187 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef _GPMUIFPERFMON_H_
23#define _GPMUIFPERFMON_H_
24
25/*perfmon task defines*/
26
27#define PMU_DOMAIN_GROUP_PSTATE 0
28#define PMU_DOMAIN_GROUP_GPC2CLK 1
29#define PMU_DOMAIN_GROUP_NUM 2
30
31#define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001)
32#define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002)
33#define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004)
34
35enum pmu_perfmon_cmd_start_fields {
36 COUNTER_ALLOC
37};
38
39enum {
40 PMU_PERFMON_CMD_ID_START = 0,
41 PMU_PERFMON_CMD_ID_STOP = 1,
42 PMU_PERFMON_CMD_ID_INIT = 2
43};
44
45struct pmu_perfmon_counter_v0 {
46 u8 index;
47 u8 flags;
48 u8 group_id;
49 u8 valid;
50 u16 upper_threshold; /* units of 0.01% */
51 u16 lower_threshold; /* units of 0.01% */
52};
53
54struct pmu_perfmon_counter_v2 {
55 u8 index;
56 u8 flags;
57 u8 group_id;
58 u8 valid;
59 u16 upper_threshold; /* units of 0.01% */
60 u16 lower_threshold; /* units of 0.01% */
61 u32 scale;
62};
63
64struct pmu_perfmon_cmd_start_v3 {
65 u8 cmd_type;
66 u8 group_id;
67 u8 state_id;
68 u8 flags;
69 struct pmu_allocation_v3 counter_alloc;
70};
71
72struct pmu_perfmon_cmd_start_v2 {
73 u8 cmd_type;
74 u8 group_id;
75 u8 state_id;
76 u8 flags;
77 struct pmu_allocation_v2 counter_alloc;
78};
79
80struct pmu_perfmon_cmd_start_v1 {
81 u8 cmd_type;
82 u8 group_id;
83 u8 state_id;
84 u8 flags;
85 struct pmu_allocation_v1 counter_alloc;
86};
87
88struct pmu_perfmon_cmd_start_v0 {
89 u8 cmd_type;
90 u8 group_id;
91 u8 state_id;
92 u8 flags;
93 struct pmu_allocation_v0 counter_alloc;
94};
95
96struct pmu_perfmon_cmd_stop {
97 u8 cmd_type;
98};
99
100struct pmu_perfmon_cmd_init_v3 {
101 u8 cmd_type;
102 u8 to_decrease_count;
103 u8 base_counter_id;
104 u32 sample_period_us;
105 struct pmu_allocation_v3 counter_alloc;
106 u8 num_counters;
107 u8 samples_in_moving_avg;
108 u16 sample_buffer;
109};
110
111struct pmu_perfmon_cmd_init_v2 {
112 u8 cmd_type;
113 u8 to_decrease_count;
114 u8 base_counter_id;
115 u32 sample_period_us;
116 struct pmu_allocation_v2 counter_alloc;
117 u8 num_counters;
118 u8 samples_in_moving_avg;
119 u16 sample_buffer;
120};
121
122struct pmu_perfmon_cmd_init_v1 {
123 u8 cmd_type;
124 u8 to_decrease_count;
125 u8 base_counter_id;
126 u32 sample_period_us;
127 struct pmu_allocation_v1 counter_alloc;
128 u8 num_counters;
129 u8 samples_in_moving_avg;
130 u16 sample_buffer;
131};
132
133struct pmu_perfmon_cmd_init_v0 {
134 u8 cmd_type;
135 u8 to_decrease_count;
136 u8 base_counter_id;
137 u32 sample_period_us;
138 struct pmu_allocation_v0 counter_alloc;
139 u8 num_counters;
140 u8 samples_in_moving_avg;
141 u16 sample_buffer;
142};
143
144struct pmu_perfmon_cmd {
145 union {
146 u8 cmd_type;
147 struct pmu_perfmon_cmd_start_v0 start_v0;
148 struct pmu_perfmon_cmd_start_v1 start_v1;
149 struct pmu_perfmon_cmd_start_v2 start_v2;
150 struct pmu_perfmon_cmd_start_v3 start_v3;
151 struct pmu_perfmon_cmd_stop stop;
152 struct pmu_perfmon_cmd_init_v0 init_v0;
153 struct pmu_perfmon_cmd_init_v1 init_v1;
154 struct pmu_perfmon_cmd_init_v2 init_v2;
155 struct pmu_perfmon_cmd_init_v3 init_v3;
156 };
157};
158
159struct pmu_zbc_cmd {
160 u8 cmd_type;
161 u8 pad;
162 u16 entry_mask;
163};
164
165/* PERFMON MSG */
166enum {
167 PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0,
168 PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1,
169 PMU_PERFMON_MSG_ID_INIT_EVENT = 2,
170 PMU_PERFMON_MSG_ID_ACK = 3
171};
172
173struct pmu_perfmon_msg_generic {
174 u8 msg_type;
175 u8 state_id;
176 u8 group_id;
177 u8 data;
178};
179
180struct pmu_perfmon_msg {
181 union {
182 u8 msg_type;
183 struct pmu_perfmon_msg_generic gen;
184 };
185};
186
187#endif /* _GPMUIFPERFMON_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 16:22:31 -0400