diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h | 249 |
1 files changed, 249 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h new file mode 100644 index 00000000..70184934 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h | |||
@@ -0,0 +1,249 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | #ifndef __ACR_LSFM_H__ | ||
23 | #define __ACR_LSFM_H__ | ||
24 | |||
25 | #ifndef __NVGPU_ACR_H__ | ||
26 | #warning "acr_lsfm.h not included from nvgpu_acr.h!" \ | ||
27 | "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" | ||
28 | #endif | ||
29 | |||
30 | /* | ||
31 | * Falcon Id Defines | ||
32 | * Defines a common Light Secure Falcon identifier. | ||
33 | */ | ||
34 | #define LSF_FALCON_ID_PMU (0) | ||
35 | #define LSF_FALCON_ID_RESERVED (1) | ||
36 | #define LSF_FALCON_ID_FECS (2) | ||
37 | #define LSF_FALCON_ID_GPCCS (3) | ||
38 | #define LSF_FALCON_ID_SEC2 (7) | ||
39 | #define LSF_FALCON_ID_END (11) | ||
40 | #define LSF_FALCON_ID_INVALID (0xFFFFFFFF) | ||
41 | |||
42 | /* | ||
43 | * Light Secure Falcon Ucode Description Defines | ||
44 | * This structure is prelim and may change as the ucode signing flow evolves. | ||
45 | */ | ||
46 | struct lsf_ucode_desc { | ||
47 | u8 prd_keys[2][16]; | ||
48 | u8 dbg_keys[2][16]; | ||
49 | u32 b_prd_present; | ||
50 | u32 b_dbg_present; | ||
51 | u32 falcon_id; | ||
52 | }; | ||
53 | |||
54 | struct lsf_ucode_desc_v1 { | ||
55 | u8 prd_keys[2][16]; | ||
56 | u8 dbg_keys[2][16]; | ||
57 | u32 b_prd_present; | ||
58 | u32 b_dbg_present; | ||
59 | u32 falcon_id; | ||
60 | u32 bsupports_versioning; | ||
61 | u32 version; | ||
62 | u32 dep_map_count; | ||
63 | u8 dep_map[LSF_FALCON_ID_END * 2 * 4]; | ||
64 | u8 kdf[16]; | ||
65 | }; | ||
66 | |||
67 | /* | ||
68 | * Light Secure WPR Header | ||
69 | * Defines state allowing Light Secure Falcon bootstrapping. | ||
70 | */ | ||
71 | struct lsf_wpr_header { | ||
72 | u32 falcon_id; | ||
73 | u32 lsb_offset; | ||
74 | u32 bootstrap_owner; | ||
75 | u32 lazy_bootstrap; | ||
76 | u32 status; | ||
77 | }; | ||
78 | |||
79 | struct lsf_wpr_header_v1 { | ||
80 | u32 falcon_id; | ||
81 | u32 lsb_offset; | ||
82 | u32 bootstrap_owner; | ||
83 | u32 lazy_bootstrap; | ||
84 | u32 bin_version; | ||
85 | u32 status; | ||
86 | }; | ||
87 | /* | ||
88 | * Bootstrap Owner Defines | ||
89 | */ | ||
90 | #define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU) | ||
91 | |||
92 | /* | ||
93 | * Image Status Defines | ||
94 | */ | ||
95 | #define LSF_IMAGE_STATUS_NONE (0) | ||
96 | #define LSF_IMAGE_STATUS_COPY (1) | ||
97 | #define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2) | ||
98 | #define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3) | ||
99 | #define LSF_IMAGE_STATUS_VALIDATION_DONE (4) | ||
100 | #define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5) | ||
101 | #define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6) | ||
102 | |||
103 | /*Light Secure Bootstrap header related defines*/ | ||
104 | #define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0 | ||
105 | #define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1 | ||
106 | #define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0 | ||
107 | #define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 4 | ||
108 | #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 8 | ||
109 | #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0 | ||
110 | |||
111 | /* | ||
112 | * Light Secure Bootstrap Header | ||
113 | * Defines state allowing Light Secure Falcon bootstrapping. | ||
114 | */ | ||
115 | struct lsf_lsb_header { | ||
116 | struct lsf_ucode_desc signature; | ||
117 | u32 ucode_off; | ||
118 | u32 ucode_size; | ||
119 | u32 data_size; | ||
120 | u32 bl_code_size; | ||
121 | u32 bl_imem_off; | ||
122 | u32 bl_data_off; | ||
123 | u32 bl_data_size; | ||
124 | u32 app_code_off; | ||
125 | u32 app_code_size; | ||
126 | u32 app_data_off; | ||
127 | u32 app_data_size; | ||
128 | u32 flags; | ||
129 | }; | ||
130 | |||
131 | struct lsf_lsb_header_v1 { | ||
132 | struct lsf_ucode_desc_v1 signature; | ||
133 | u32 ucode_off; | ||
134 | u32 ucode_size; | ||
135 | u32 data_size; | ||
136 | u32 bl_code_size; | ||
137 | u32 bl_imem_off; | ||
138 | u32 bl_data_off; | ||
139 | u32 bl_data_size; | ||
140 | u32 app_code_off; | ||
141 | u32 app_code_size; | ||
142 | u32 app_data_off; | ||
143 | u32 app_data_size; | ||
144 | u32 flags; | ||
145 | }; | ||
146 | |||
147 | /* | ||
148 | * Light Secure WPR Content Alignments | ||
149 | */ | ||
150 | #define LSF_LSB_HEADER_ALIGNMENT 256 | ||
151 | #define LSF_BL_DATA_ALIGNMENT 256 | ||
152 | #define LSF_BL_DATA_SIZE_ALIGNMENT 256 | ||
153 | #define LSF_BL_CODE_SIZE_ALIGNMENT 256 | ||
154 | |||
155 | #define LSF_UCODE_DATA_ALIGNMENT 4096 | ||
156 | |||
157 | /* | ||
158 | * Supporting maximum of 2 regions. | ||
159 | * This is needed to pre-allocate space in DMEM | ||
160 | */ | ||
161 | #define NVGPU_FLCN_ACR_MAX_REGIONS (2) | ||
162 | #define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200) | ||
163 | |||
164 | /* | ||
165 | * start_addr - Starting address of region | ||
166 | * end_addr - Ending address of region | ||
167 | * region_id - Region ID | ||
168 | * read_mask - Read Mask | ||
169 | * write_mask - WriteMask | ||
170 | * client_mask - Bit map of all clients currently using this region | ||
171 | */ | ||
172 | struct flcn_acr_region_prop { | ||
173 | u32 start_addr; | ||
174 | u32 end_addr; | ||
175 | u32 region_id; | ||
176 | u32 read_mask; | ||
177 | u32 write_mask; | ||
178 | u32 client_mask; | ||
179 | }; | ||
180 | |||
181 | struct flcn_acr_region_prop_v1 { | ||
182 | u32 start_addr; | ||
183 | u32 end_addr; | ||
184 | u32 region_id; | ||
185 | u32 read_mask; | ||
186 | u32 write_mask; | ||
187 | u32 client_mask; | ||
188 | u32 shadowmMem_startaddress; | ||
189 | }; | ||
190 | |||
191 | /* | ||
192 | * no_regions - Number of regions used. | ||
193 | * region_props - Region properties | ||
194 | */ | ||
195 | struct flcn_acr_regions { | ||
196 | u32 no_regions; | ||
197 | struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS]; | ||
198 | }; | ||
199 | |||
200 | struct flcn_acr_regions_v1 { | ||
201 | u32 no_regions; | ||
202 | struct flcn_acr_region_prop_v1 region_props[NVGPU_FLCN_ACR_MAX_REGIONS]; | ||
203 | }; | ||
204 | /* | ||
205 | * reserved_dmem-When the bootstrap owner has done bootstrapping other falcons, | ||
206 | * and need to switch into LS mode, it needs to have its own | ||
207 | * actual DMEM image copied into DMEM as part of LS setup. If | ||
208 | * ACR desc is at location 0, it will definitely get overwritten | ||
209 | * causing data corruption. Hence we are reserving 0x200 bytes | ||
210 | * to give room for any loading data. NOTE: This has to be the | ||
211 | * first member always | ||
212 | * signature - Signature of ACR ucode. | ||
213 | * wpr_region_id - Region ID holding the WPR header and its details | ||
214 | * wpr_offset - Offset from the WPR region holding the wpr header | ||
215 | * regions - Region descriptors | ||
216 | * nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob | ||
217 | * nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob | ||
218 | */ | ||
219 | struct flcn_acr_desc { | ||
220 | union { | ||
221 | u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; | ||
222 | u32 signatures[4]; | ||
223 | } ucode_reserved_space; | ||
224 | /*Always 1st*/ | ||
225 | u32 wpr_region_id; | ||
226 | u32 wpr_offset; | ||
227 | u32 mmu_mem_range; | ||
228 | struct flcn_acr_regions regions; | ||
229 | u32 nonwpr_ucode_blob_size; | ||
230 | u64 nonwpr_ucode_blob_start; | ||
231 | }; | ||
232 | |||
233 | struct flcn_acr_desc_v1 { | ||
234 | union { | ||
235 | u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; | ||
236 | } ucode_reserved_space; | ||
237 | u32 signatures[4]; | ||
238 | /*Always 1st*/ | ||
239 | u32 wpr_region_id; | ||
240 | u32 wpr_offset; | ||
241 | u32 mmu_mem_range; | ||
242 | struct flcn_acr_regions_v1 regions; | ||
243 | u32 nonwpr_ucode_blob_size; | ||
244 | u64 nonwpr_ucode_blob_start; | ||
245 | u32 dummy[4]; /* ACR_BSI_VPR_DESC */ | ||
246 | }; | ||
247 | |||
248 | |||
249 | #endif /* __ACR_LSFM_H__ */ | ||