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path: root/drivers/gpu/nvgpu/include/bios.h
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Diffstat (limited to 'drivers/gpu/nvgpu/include/bios.h')
-rw-r--r--drivers/gpu/nvgpu/include/bios.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/bios.h
index 097e90ec..bcb24343 100644
--- a/drivers/gpu/nvgpu/include/bios.h
+++ b/drivers/gpu/nvgpu/include/bios.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * vbios tables support 2 * vbios tables support
3 * 3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -510,7 +510,7 @@ struct pwr_sensors_2x_header {
510 u8 table_entry_size; 510 u8 table_entry_size;
511 u8 num_table_entries; 511 u8 num_table_entries;
512 u32 ba_script_pointer; 512 u32 ba_script_pointer;
513}; 513} __packed;
514 514
515#define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 0x00000015 515#define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 0x00000015
516 516
@@ -521,7 +521,7 @@ struct pwr_sensors_2x_entry {
521 u32 sensor_param1; 521 u32 sensor_param1;
522 u32 sensor_param2; 522 u32 sensor_param2;
523 u32 sensor_param3; 523 u32 sensor_param3;
524}; 524} __packed;
525 525
526#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xF 526#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xF
527#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 527#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0
@@ -560,7 +560,7 @@ struct pwr_topology_2x_header {
560 u8 num_table_entries; 560 u8 num_table_entries;
561 u8 rel_entry_size; 561 u8 rel_entry_size;
562 u8 num_rel_entries; 562 u8 num_rel_entries;
563}; 563} __packed;
564 564
565#define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 0x00000016 565#define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 0x00000016
566 566
@@ -572,7 +572,7 @@ struct pwr_topology_2x_entry {
572 u32 curr_corr_offset; 572 u32 curr_corr_offset;
573 u32 param1; 573 u32 param1;
574 u32 param2; 574 u32 param2;
575}; 575} __packed;
576 576
577#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xF 577#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xF
578#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 578#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0
@@ -609,7 +609,7 @@ struct pwr_policy_3x_header_struct {
609 u8 sm_bus_policy_idx; 609 u8 sm_bus_policy_idx;
610 u8 table_viol_entry_size; 610 u8 table_viol_entry_size;
611 u8 num_table_viol_entries; 611 u8 num_table_viol_entries;
612}; 612} __packed;
613 613
614#define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E 0x0000002E 614#define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E 0x0000002E
615 615
@@ -631,7 +631,7 @@ struct pwr_policy_3x_entry_struct {
631 u16 ratio_max; 631 u16 ratio_max;
632 u8 sample_mult; 632 u8 sample_mult;
633 u32 filter_param; 633 u32 filter_param;
634}; 634} __packed;
635 635
636#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xF 636#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xF
637#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0 637#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0