diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include/bios.h')
-rw-r--r-- | drivers/gpu/nvgpu/include/bios.h | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/bios.h index 02991db9..f3939d14 100644 --- a/drivers/gpu/nvgpu/include/bios.h +++ b/drivers/gpu/nvgpu/include/bios.h | |||
@@ -842,4 +842,87 @@ struct therm_channel_1x_entry { | |||
842 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_MASK 0xFF | 842 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_MASK 0xFF |
843 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_SHIFT 0 | 843 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_SHIFT 0 |
844 | 844 | ||
845 | /* Frequency Controller Table */ | ||
846 | struct vbios_fct_1x_header { | ||
847 | u8 version; | ||
848 | u8 header_size; | ||
849 | u8 entry_size; | ||
850 | u8 entry_count; | ||
851 | u16 sampling_period_ms; | ||
852 | } __packed; | ||
853 | |||
854 | struct vbios_fct_1x_entry { | ||
855 | u8 flags0; | ||
856 | u8 clk_domain_idx; | ||
857 | u16 param0; | ||
858 | u16 param1; | ||
859 | u32 param2; | ||
860 | u32 param3; | ||
861 | u32 param4; | ||
862 | u32 param5; | ||
863 | u32 param6; | ||
864 | u32 param7; | ||
865 | u32 param8; | ||
866 | } __packed; | ||
867 | |||
868 | #define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_MASK GENMASK(3, 0) | ||
869 | #define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 | ||
870 | #define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_DISABLED 0x0 | ||
871 | #define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_PI 0x1 | ||
872 | |||
873 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_MASK GENMASK(7, 0) | ||
874 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SHIFT 0 | ||
875 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SYS 0x00 | ||
876 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_LTC 0x01 | ||
877 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_XBAR 0x02 | ||
878 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC0 0x03 | ||
879 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC1 0x04 | ||
880 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC2 0x05 | ||
881 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC3 0x06 | ||
882 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC4 0x07 | ||
883 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC5 0x08 | ||
884 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPCS 0x09 | ||
885 | |||
886 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MASK GENMASK(9, 8) | ||
887 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_SHIFT 8 | ||
888 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_BCAST 0x0 | ||
889 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MIN 0x1 | ||
890 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MAX 0x2 | ||
891 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_AVG 0x3 | ||
892 | |||
893 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_MASK GENMASK(7, 0) | ||
894 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_SHIFT 0 | ||
895 | |||
896 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_MASK GENMASK(8, 8) | ||
897 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_SHIFT 8 | ||
898 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_NO 0x0 | ||
899 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_YES 0x1 | ||
900 | |||
901 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_MASK GENMASK(31, 0) | ||
902 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_SHIFT 0 | ||
903 | |||
904 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_MASK GENMASK(31, 0) | ||
905 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_SHIFT 0 | ||
906 | |||
907 | |||
908 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_MASK GENMASK(31, 0) | ||
909 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_SHIFT 0 | ||
910 | |||
911 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_MASK GENMASK(31, 0) | ||
912 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_SHIFT 0 | ||
913 | |||
914 | |||
915 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_MASK GENMASK(31, 0) | ||
916 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_SHIFT 0 | ||
917 | |||
918 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_MASK GENMASK(15, 0) | ||
919 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_SHIFT 0 | ||
920 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_MASK GENMASK(31, 16) | ||
921 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_SHIFT 16 | ||
922 | |||
923 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_MASK GENMASK(15, 0) | ||
924 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_SHIFT 0 | ||
925 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_MASK GENMASK(31, 16) | ||
926 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_SHIFT 16 | ||
927 | |||
845 | #endif | 928 | #endif |