diff options
Diffstat (limited to 'drivers/gpu/nvgpu/include/bios.h')
-rw-r--r-- | drivers/gpu/nvgpu/include/bios.h | 992 |
1 files changed, 0 insertions, 992 deletions
diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/bios.h deleted file mode 100644 index bcb24343..00000000 --- a/drivers/gpu/nvgpu/include/bios.h +++ /dev/null | |||
@@ -1,992 +0,0 @@ | |||
1 | /* | ||
2 | * vbios tables support | ||
3 | * | ||
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef NVGPU_INCLUDE_BIOS_H | ||
17 | #define NVGPU_INCLUDE_BIOS_H | ||
18 | |||
19 | #include "gk20a/gk20a.h" | ||
20 | |||
21 | #define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT) | ||
22 | |||
23 | struct fll_descriptor_header { | ||
24 | u8 version; | ||
25 | u8 size; | ||
26 | } __packed; | ||
27 | |||
28 | #define FLL_DESCRIPTOR_HEADER_10_SIZE_4 4 | ||
29 | #define FLL_DESCRIPTOR_HEADER_10_SIZE_6 6 | ||
30 | |||
31 | struct fll_descriptor_header_10 { | ||
32 | u8 version; | ||
33 | u8 header_size; | ||
34 | u8 entry_size; | ||
35 | u8 entry_count; | ||
36 | u16 max_min_freq_mhz; | ||
37 | } __packed; | ||
38 | |||
39 | #define FLL_DESCRIPTOR_ENTRY_10_SIZE 15 | ||
40 | |||
41 | struct fll_descriptor_entry_10 { | ||
42 | u8 fll_device_type; | ||
43 | u8 clk_domain; | ||
44 | u8 fll_device_id; | ||
45 | u16 lut_params; | ||
46 | u8 vin_idx_logic; | ||
47 | u8 vin_idx_sram; | ||
48 | u16 fll_params; | ||
49 | u8 min_freq_vfe_idx; | ||
50 | u8 freq_ctrl_idx; | ||
51 | u16 ref_freq_mhz; | ||
52 | u16 ffr_cutoff_freq_mhz; | ||
53 | } __packed; | ||
54 | |||
55 | #define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F | ||
56 | #define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0 | ||
57 | |||
58 | #define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3 | ||
59 | #define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0 | ||
60 | |||
61 | #define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_MASK 0x3C | ||
62 | #define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_SHIFT 2 | ||
63 | |||
64 | struct vin_descriptor_header_10 { | ||
65 | u8 version; | ||
66 | u8 header_sizee; | ||
67 | u8 entry_size; | ||
68 | u8 entry_count; | ||
69 | u8 flags0; | ||
70 | u32 vin_cal; | ||
71 | } __packed; | ||
72 | |||
73 | struct vin_descriptor_entry_10 { | ||
74 | u8 vin_device_type; | ||
75 | u8 volt_domain_vbios; | ||
76 | u8 vin_device_id; | ||
77 | } __packed; | ||
78 | |||
79 | #define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7 | ||
80 | #define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0 | ||
81 | |||
82 | #define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8 | ||
83 | #define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3 | ||
84 | |||
85 | #define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_MASK 0x1FF | ||
86 | #define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_SHIFT 0 | ||
87 | |||
88 | #define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_MASK 0x3C00 | ||
89 | #define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_SHIFT 10 | ||
90 | |||
91 | #define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_MASK 0x3C000 | ||
92 | #define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_SHIFT 14 | ||
93 | |||
94 | #define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000 | ||
95 | #define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18 | ||
96 | |||
97 | #define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07 | ||
98 | struct vbios_clocks_table_1x_header { | ||
99 | u8 version; | ||
100 | u8 header_size; | ||
101 | u8 entry_size; | ||
102 | u8 entry_count; | ||
103 | u8 clocks_hal; | ||
104 | u16 cntr_sampling_periodms; | ||
105 | } __packed; | ||
106 | |||
107 | #define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09 | ||
108 | struct vbios_clocks_table_1x_entry { | ||
109 | u8 flags0; | ||
110 | u16 param0; | ||
111 | u32 param1; | ||
112 | u16 param2; | ||
113 | } __packed; | ||
114 | |||
115 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK 0x1F | ||
116 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT 0 | ||
117 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED 0x00 | ||
118 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER 0x01 | ||
119 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE 0x02 | ||
120 | |||
121 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_MASK 0xFF | ||
122 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_SHIFT 0 | ||
123 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_MASK 0xFF00 | ||
124 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_SHIFT 0x08 | ||
125 | |||
126 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_MASK 0xFFFF | ||
127 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_SHIFT 0 | ||
128 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_MASK 0xFFFF | ||
129 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_SHIFT 0 | ||
130 | |||
131 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_MASK 0xFFFF0000 | ||
132 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_SHIFT 0 | ||
133 | |||
134 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_MASK 0xF | ||
135 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_SHIFT 0 | ||
136 | |||
137 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_MASK 0xF | ||
138 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_SHIFT 0 | ||
139 | |||
140 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_MASK 0xF0 | ||
141 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_SHIFT 4 | ||
142 | |||
143 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_MASK 0x100 | ||
144 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_SHIFT 8 | ||
145 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE 0x00 | ||
146 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE 0x01 | ||
147 | |||
148 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08 | ||
149 | struct vbios_clock_programming_table_1x_header { | ||
150 | u8 version; | ||
151 | u8 header_size; | ||
152 | u8 entry_size; | ||
153 | u8 entry_count; | ||
154 | u8 slave_entry_size; | ||
155 | u8 slave_entry_count; | ||
156 | u8 vf_entry_size; | ||
157 | u8 vf_entry_count; | ||
158 | } __packed; | ||
159 | |||
160 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05 0x05 | ||
161 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D 0x0D | ||
162 | struct vbios_clock_programming_table_1x_entry { | ||
163 | u8 flags0; | ||
164 | u16 freq_max_mhz; | ||
165 | u8 param0; | ||
166 | u8 param1; | ||
167 | u32 rsvd; | ||
168 | u32 rsvd1; | ||
169 | } __packed; | ||
170 | |||
171 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASK 0xF | ||
172 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 | ||
173 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO 0x00 | ||
174 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_TABLE 0x01 | ||
175 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SLAVE 0x02 | ||
176 | |||
177 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_MASK 0x70 | ||
178 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_SHIFT 4 | ||
179 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_PLL 0x00 | ||
180 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_ONE_SOURCE 0x01 | ||
181 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_FLL 0x02 | ||
182 | |||
183 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_MASK 0x80 | ||
184 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_SHIFT 7 | ||
185 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_FALSE 0x00 | ||
186 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_TRUE 0x01 | ||
187 | |||
188 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_MASK 0xFF | ||
189 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_SHIFT 0 | ||
190 | |||
191 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK 0xFF | ||
192 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT 0 | ||
193 | |||
194 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03 0x03 | ||
195 | struct vbios_clock_programming_table_1x_slave_entry { | ||
196 | u8 clk_dom_idx; | ||
197 | u16 param0; | ||
198 | } __packed; | ||
199 | |||
200 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_MASK 0xFF | ||
201 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_SHIFT 0 | ||
202 | |||
203 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_MASK 0x3FFF | ||
204 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_SHIFT 0 | ||
205 | |||
206 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02 0x02 | ||
207 | struct vbios_clock_programming_table_1x_vf_entry { | ||
208 | u8 vfe_idx; | ||
209 | u8 param0; | ||
210 | } __packed; | ||
211 | |||
212 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_MASK 0xFF | ||
213 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_SHIFT 0 | ||
214 | |||
215 | struct vbios_vfe_3x_header_struct { | ||
216 | u8 version; | ||
217 | u8 header_size; | ||
218 | u8 vfe_var_entry_size; | ||
219 | u8 vfe_var_entry_count; | ||
220 | u8 vfe_equ_entry_size; | ||
221 | u8 vfe_equ_entry_count; | ||
222 | u8 polling_periodms; | ||
223 | } __packed; | ||
224 | |||
225 | #define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11 0x11 | ||
226 | #define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19 0x19 | ||
227 | struct vbios_vfe_3x_var_entry_struct { | ||
228 | u8 type; | ||
229 | u32 out_range_min; | ||
230 | u32 out_range_max; | ||
231 | u32 param0; | ||
232 | u32 param1; | ||
233 | u32 param2; | ||
234 | u32 param3; | ||
235 | } __packed; | ||
236 | |||
237 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED 0x00 | ||
238 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_FREQUENCY 0x01 | ||
239 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_VOLTAGE 0x02 | ||
240 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_TEMP 0x03 | ||
241 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE 0x04 | ||
242 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT 0x05 | ||
243 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM 0x06 | ||
244 | |||
245 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFF | ||
246 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0 | ||
247 | |||
248 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_MASK 0xFF00 | ||
249 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_SHIFT 8 | ||
250 | |||
251 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_MASK 0xFF0000 | ||
252 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_SHIFT 16 | ||
253 | |||
254 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_MASK 0xFF | ||
255 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_SHIFT 0 | ||
256 | |||
257 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_MASK 0xFF00 | ||
258 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_SHIFT 8 | ||
259 | |||
260 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_MASK 0xFF0000 | ||
261 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_SHIFT 16 | ||
262 | |||
263 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000 | ||
264 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24 | ||
265 | |||
266 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001 | ||
267 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000 | ||
268 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF | ||
269 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_SHIFT 0 | ||
270 | |||
271 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_MASK 0xFF00 | ||
272 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_SHIFT 8 | ||
273 | |||
274 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_MASK 0xFF | ||
275 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_SHIFT 0 | ||
276 | |||
277 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_MASK 0xFF00 | ||
278 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_SHIFT 8 | ||
279 | |||
280 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_MASK 0xFFFFFFFF | ||
281 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_SHIFT 0 | ||
282 | |||
283 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_MASK 0xFFFFFFFF | ||
284 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_SHIFT 0 | ||
285 | |||
286 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFF | ||
287 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0 | ||
288 | |||
289 | #define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17 0x17 | ||
290 | #define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18 0x18 | ||
291 | |||
292 | struct vbios_vfe_3x_equ_entry_struct { | ||
293 | u8 type; | ||
294 | u8 var_idx; | ||
295 | u8 equ_idx_next; | ||
296 | u32 out_range_min; | ||
297 | u32 out_range_max; | ||
298 | u32 param0; | ||
299 | u32 param1; | ||
300 | u32 param2; | ||
301 | u8 param3; | ||
302 | } __packed; | ||
303 | |||
304 | |||
305 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_DISABLED 0x00 | ||
306 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC 0x01 | ||
307 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX 0x02 | ||
308 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE 0x03 | ||
309 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC_FXP 0x04 | ||
310 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX_FXP 0x05 | ||
311 | |||
312 | #define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID 0xFF | ||
313 | |||
314 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFF | ||
315 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0 | ||
316 | |||
317 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_MASK 0xFF | ||
318 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_SHIFT 0 | ||
319 | |||
320 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_MASK 0xFF00 | ||
321 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_SHIFT 8 | ||
322 | |||
323 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MASK 0x10000 | ||
324 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_SHIFT 16 | ||
325 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MIN 0x00000000 | ||
326 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX 0x00000001 | ||
327 | |||
328 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_MASK 0xFFFFFFFF | ||
329 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_SHIFT 0 | ||
330 | |||
331 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_MASK 0xFFFFFFFF | ||
332 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_SHIFT 0 | ||
333 | |||
334 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_MASK 0xFF | ||
335 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_SHIFT 0 | ||
336 | |||
337 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_MASK 0xFF00 | ||
338 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_SHIFT 8 | ||
339 | |||
340 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_MASK 0x70000 | ||
341 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_SHIFT 16 | ||
342 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_EQUAL 0x00000000 | ||
343 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER_EQ 0x00000001 | ||
344 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER 0x00000002 | ||
345 | |||
346 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_MASK 0xF | ||
347 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_SHIFT 0 | ||
348 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_UNITLESS 0x0 | ||
349 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_FREQ_MHZ 0x1 | ||
350 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_UV 0x2 | ||
351 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN 0x3 | ||
352 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV 0x4 | ||
353 | |||
354 | #define NV_VFIELD_DESC_SIZE_BYTE 0x00000000 | ||
355 | #define NV_VFIELD_DESC_SIZE_WORD 0x00000001 | ||
356 | #define NV_VFIELD_DESC_SIZE_DWORD 0x00000002 | ||
357 | #define VFIELD_SIZE(pvregentry) ((pvregentry->strap_reg_desc & 0x18) >> 3) | ||
358 | |||
359 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID 0x00000000 | ||
360 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_REG 0x00000001 | ||
361 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG 0x00000002 | ||
362 | |||
363 | #define NV_VFIELD_DESC_CODE_INVALID NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID | ||
364 | #define NV_VFIELD_DESC_CODE_REG NV_PMU_BIOS_VFIELD_DESC_CODE_REG | ||
365 | #define NV_VFIELD_DESC_CODE_INDEX_REG NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG | ||
366 | |||
367 | #define VFIELD_CODE(pvregentry) ((pvregentry->strap_reg_desc & 0xE0) >> 5) | ||
368 | |||
369 | #define VFIELD_ID_STRAP_IDDQ 0x09 | ||
370 | #define VFIELD_ID_STRAP_IDDQ_1 0x0B | ||
371 | |||
372 | #define VFIELD_REG_HEADER_SIZE 3 | ||
373 | struct vfield_reg_header { | ||
374 | u8 version; | ||
375 | u8 entry_size; | ||
376 | u8 count; | ||
377 | } __packed; | ||
378 | |||
379 | #define VBIOS_VFIELD_REG_TABLE_VERSION_1_0 0x10 | ||
380 | |||
381 | |||
382 | #define VFIELD_REG_ENTRY_SIZE 13 | ||
383 | struct vfield_reg_entry { | ||
384 | u8 strap_reg_desc; | ||
385 | u32 reg; | ||
386 | u32 reg_index; | ||
387 | u32 index; | ||
388 | } __packed; | ||
389 | |||
390 | #define VFIELD_HEADER_SIZE 3 | ||
391 | |||
392 | struct vfield_header { | ||
393 | u8 version; | ||
394 | u8 entry_size; | ||
395 | u8 count; | ||
396 | } __packed; | ||
397 | |||
398 | #define VBIOS_VFIELD_TABLE_VERSION_1_0 0x10 | ||
399 | |||
400 | #define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1F) | ||
401 | #define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0) >> 5) | ||
402 | #define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00) >> 10) | ||
403 | |||
404 | #define VFIELD_ENTRY_SIZE 3 | ||
405 | |||
406 | struct vfield_entry { | ||
407 | u8 strap_id; | ||
408 | u16 strap_desc; | ||
409 | } __packed; | ||
410 | |||
411 | #define PERF_CLK_DOMAINS_IDX_MAX (32) | ||
412 | #define PERF_CLK_DOMAINS_IDX_INVALID PERF_CLK_DOMAINS_IDX_MAX | ||
413 | |||
414 | #define VBIOS_PSTATE_TABLE_VERSION_5X 0x50 | ||
415 | #define VBIOS_PSTATE_HEADER_5X_SIZE_10 (10) | ||
416 | |||
417 | struct vbios_pstate_header_5x { | ||
418 | u8 version; | ||
419 | u8 header_size; | ||
420 | u8 base_entry_size; | ||
421 | u8 base_entry_count; | ||
422 | u8 clock_entry_size; | ||
423 | u8 clock_entry_count; | ||
424 | u8 flags0; | ||
425 | u8 initial_pstate; | ||
426 | u8 cpi_support_level; | ||
427 | u8 cpi_features; | ||
428 | } __packed; | ||
429 | |||
430 | #define VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6 6 | ||
431 | |||
432 | #define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2 0x2 | ||
433 | #define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3 0x3 | ||
434 | |||
435 | struct vbios_pstate_entry_clock_5x { | ||
436 | u16 param0; | ||
437 | u32 param1; | ||
438 | } __packed; | ||
439 | |||
440 | struct vbios_pstate_entry_5x { | ||
441 | u8 pstate_level; | ||
442 | u8 flags0; | ||
443 | u8 lpwr_entry_idx; | ||
444 | struct vbios_pstate_entry_clock_5x clockEntry[PERF_CLK_DOMAINS_IDX_MAX]; | ||
445 | } __packed; | ||
446 | |||
447 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_SHIFT 0 | ||
448 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_MASK 0x00003FFF | ||
449 | |||
450 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_SHIFT 0 | ||
451 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_MASK 0x00003FFF | ||
452 | |||
453 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_SHIFT 14 | ||
454 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_MASK 0x0FFFC000 | ||
455 | |||
456 | #define VBIOS_PERFLEVEL_SKIP_ENTRY 0xFF | ||
457 | |||
458 | #define VBIOS_MEMORY_CLOCK_HEADER_11_VERSION 0x11 | ||
459 | |||
460 | #define VBIOS_MEMORY_CLOCK_HEADER_11_0_SIZE 16 | ||
461 | #define VBIOS_MEMORY_CLOCK_HEADER_11_1_SIZE 21 | ||
462 | #define VBIOS_MEMORY_CLOCK_HEADER_11_2_SIZE 26 | ||
463 | |||
464 | struct vbios_memory_clock_header_1x { | ||
465 | u8 version; | ||
466 | u8 header_size; | ||
467 | u8 base_entry_size; | ||
468 | u8 strap_entry_size; | ||
469 | u8 strap_entry_count; | ||
470 | u8 entry_count; | ||
471 | u8 flags; | ||
472 | u8 fbvdd_settle_time; | ||
473 | u32 cfg_pwrd_val; | ||
474 | u16 fbvddq_high; | ||
475 | u16 fbvddq_low; | ||
476 | u32 script_list_ptr; | ||
477 | u8 script_list_count; | ||
478 | u32 cmd_script_list_ptr; | ||
479 | u8 cmd_script_list_count; | ||
480 | } __packed; | ||
481 | |||
482 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_2_SIZE 20 | ||
483 | |||
484 | struct vbios_memory_clock_base_entry_11 { | ||
485 | u16 minimum; | ||
486 | u16 maximum; | ||
487 | u32 script_pointer; | ||
488 | u8 flags0; | ||
489 | u32 fbpa_config; | ||
490 | u32 fbpa_config1; | ||
491 | u8 flags1; | ||
492 | u8 ref_mpllssf_freq_delta; | ||
493 | u8 flags2; | ||
494 | } __packed; | ||
495 | |||
496 | /* Script Pointer Index */ | ||
497 | /* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX 3:2*/ | ||
498 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_MASK 0xc | ||
499 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_SHIFT 2 | ||
500 | /* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX 1:0*/ | ||
501 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK 0x3 | ||
502 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 | ||
503 | |||
504 | #define VBIOS_POWER_SENSORS_VERSION_2X 0x20 | ||
505 | #define VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08 0x00000008 | ||
506 | |||
507 | struct pwr_sensors_2x_header { | ||
508 | u8 version; | ||
509 | u8 header_size; | ||
510 | u8 table_entry_size; | ||
511 | u8 num_table_entries; | ||
512 | u32 ba_script_pointer; | ||
513 | } __packed; | ||
514 | |||
515 | #define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 0x00000015 | ||
516 | |||
517 | struct pwr_sensors_2x_entry { | ||
518 | u8 flags0; | ||
519 | u32 class_param0; | ||
520 | u32 sensor_param0; | ||
521 | u32 sensor_param1; | ||
522 | u32 sensor_param2; | ||
523 | u32 sensor_param3; | ||
524 | } __packed; | ||
525 | |||
526 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xF | ||
527 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 | ||
528 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C 0x00000001 | ||
529 | |||
530 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_MASK 0xFF | ||
531 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_SHIFT 0 | ||
532 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_MASK 0x100 | ||
533 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_SHIFT 8 | ||
534 | |||
535 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_MASK 0xFFFF | ||
536 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_SHIFT 0 | ||
537 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_MASK 0xFFFF0000 | ||
538 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_SHIFT 16 | ||
539 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_MASK 0xFFFF | ||
540 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_SHIFT 0 | ||
541 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_MASK 0xFFFF0000 | ||
542 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_SHIFT 16 | ||
543 | |||
544 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_MASK 0xFFFF | ||
545 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_SHIFT 0 | ||
546 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_MASK 0xFF0000 | ||
547 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_SHIFT 16 | ||
548 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_MASK 0xFFFF | ||
549 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_SHIFT 0 | ||
550 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_MASK 0xFFFF0000 | ||
551 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_SHIFT 16 | ||
552 | |||
553 | #define VBIOS_POWER_TOPOLOGY_VERSION_2X 0x20 | ||
554 | #define VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06 0x00000006 | ||
555 | |||
556 | struct pwr_topology_2x_header { | ||
557 | u8 version; | ||
558 | u8 header_size; | ||
559 | u8 table_entry_size; | ||
560 | u8 num_table_entries; | ||
561 | u8 rel_entry_size; | ||
562 | u8 num_rel_entries; | ||
563 | } __packed; | ||
564 | |||
565 | #define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 0x00000016 | ||
566 | |||
567 | struct pwr_topology_2x_entry { | ||
568 | u8 flags0; | ||
569 | u8 pwr_rail; | ||
570 | u32 param0; | ||
571 | u32 curr_corr_slope; | ||
572 | u32 curr_corr_offset; | ||
573 | u32 param1; | ||
574 | u32 param2; | ||
575 | } __packed; | ||
576 | |||
577 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xF | ||
578 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 | ||
579 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR 0x00000001 | ||
580 | |||
581 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_MASK 0xFF | ||
582 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_SHIFT 0 | ||
583 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_MASK 0xFF00 | ||
584 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_SHIFT 8 | ||
585 | |||
586 | #define VBIOS_POWER_POLICY_VERSION_3X 0x30 | ||
587 | #define VBIOS_POWER_POLICY_3X_HEADER_SIZE_25 0x00000025 | ||
588 | |||
589 | struct pwr_policy_3x_header_struct { | ||
590 | u8 version; | ||
591 | u8 header_size; | ||
592 | u8 table_entry_size; | ||
593 | u8 num_table_entries; | ||
594 | u16 base_sample_period; | ||
595 | u16 min_client_sample_period; | ||
596 | u8 table_rel_entry_size; | ||
597 | u8 num_table_rel_entries; | ||
598 | u8 tgp_policy_idx; | ||
599 | u8 rtp_policy_idx; | ||
600 | u8 mxm_policy_idx; | ||
601 | u8 dnotifier_policy_idx; | ||
602 | u32 d2_limit; | ||
603 | u32 d3_limit; | ||
604 | u32 d4_limit; | ||
605 | u32 d5_limit; | ||
606 | u8 low_sampling_mult; | ||
607 | u8 pwr_tgt_policy_idx; | ||
608 | u8 pwr_tgt_floor_policy_idx; | ||
609 | u8 sm_bus_policy_idx; | ||
610 | u8 table_viol_entry_size; | ||
611 | u8 num_table_viol_entries; | ||
612 | } __packed; | ||
613 | |||
614 | #define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E 0x0000002E | ||
615 | |||
616 | struct pwr_policy_3x_entry_struct { | ||
617 | u8 flags0; | ||
618 | u8 ch_idx; | ||
619 | u32 limit_min; | ||
620 | u32 limit_rated; | ||
621 | u32 limit_max; | ||
622 | u32 param0; | ||
623 | u32 param1; | ||
624 | u32 param2; | ||
625 | u32 param3; | ||
626 | u32 limit_batt; | ||
627 | u8 flags1; | ||
628 | u8 past_length; | ||
629 | u8 next_length; | ||
630 | u16 ratio_min; | ||
631 | u16 ratio_max; | ||
632 | u8 sample_mult; | ||
633 | u32 filter_param; | ||
634 | } __packed; | ||
635 | |||
636 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xF | ||
637 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0 | ||
638 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD 0x00000005 | ||
639 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_MASK 0x10 | ||
640 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_SHIFT 4 | ||
641 | |||
642 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_MASK 0x1 | ||
643 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_SHIFT 0 | ||
644 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_MASK 0x2 | ||
645 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_SHIFT 1 | ||
646 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_MASK 0x3C | ||
647 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_SHIFT 2 | ||
648 | |||
649 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_MASK 0xFF | ||
650 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_SHIFT 0 | ||
651 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_MASK 0xFF00 | ||
652 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_SHIFT 8 | ||
653 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_MASK 0x10000 | ||
654 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_SHIFT 16 | ||
655 | |||
656 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF | ||
657 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0 | ||
658 | |||
659 | /* Voltage Rail Table */ | ||
660 | struct vbios_voltage_rail_table_1x_header { | ||
661 | u8 version; | ||
662 | u8 header_size; | ||
663 | u8 table_entry_size; | ||
664 | u8 num_table_entries; | ||
665 | u8 volt_domain_hal; | ||
666 | } __packed; | ||
667 | |||
668 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07 0X00000007 | ||
669 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08 0X00000008 | ||
670 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009 | ||
671 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000A | ||
672 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000B | ||
673 | |||
674 | struct vbios_voltage_rail_table_1x_entry { | ||
675 | u32 boot_voltage_uv; | ||
676 | u8 rel_limit_vfe_equ_idx; | ||
677 | u8 alt_rel_limit_vfe_equidx; | ||
678 | u8 ov_limit_vfe_equ_idx; | ||
679 | u8 pwr_equ_idx; | ||
680 | u8 boot_volt_vfe_equ_idx; | ||
681 | u8 vmin_limit_vfe_equ_idx; | ||
682 | u8 volt_margin_limit_vfe_equ_idx; | ||
683 | } __packed; | ||
684 | |||
685 | /* Voltage Device Table */ | ||
686 | struct vbios_voltage_device_table_1x_header { | ||
687 | u8 version; | ||
688 | u8 header_size; | ||
689 | u8 table_entry_size; | ||
690 | u8 num_table_entries; | ||
691 | }; | ||
692 | |||
693 | struct vbios_voltage_device_table_1x_entry { | ||
694 | u8 type; | ||
695 | u8 volt_domain; | ||
696 | u16 settle_time_us; | ||
697 | u32 param0; | ||
698 | u32 param1; | ||
699 | u32 param2; | ||
700 | u32 param3; | ||
701 | u32 param4; | ||
702 | }; | ||
703 | |||
704 | #define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID 0x00 | ||
705 | #define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV 0x02 | ||
706 | |||
707 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK \ | ||
708 | GENMASK(23, 0) | ||
709 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_SHIFT 0 | ||
710 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_MASK \ | ||
711 | GENMASK(31, 24) | ||
712 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_SHIFT 24 | ||
713 | |||
714 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_MASK \ | ||
715 | GENMASK(23, 0) | ||
716 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_SHIFT 0 | ||
717 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_MASK \ | ||
718 | GENMASK(31, 24) | ||
719 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_SHIFT 24 | ||
720 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT 0x00 | ||
721 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE \ | ||
722 | 0x01 | ||
723 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE \ | ||
724 | 0x02 | ||
725 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_MASK \ | ||
726 | GENMASK(23, 0) | ||
727 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_SHIFT 0 | ||
728 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_MASK \ | ||
729 | GENMASK(31, 24) | ||
730 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_SHIFT 24 | ||
731 | |||
732 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_MASK \ | ||
733 | GENMASK(23, 0) | ||
734 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_SHIFT 0 | ||
735 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_MASK \ | ||
736 | GENMASK(31, 24) | ||
737 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_SHIFT 24 | ||
738 | |||
739 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_MASK \ | ||
740 | GENMASK(23, 0) | ||
741 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_SHIFT 0 | ||
742 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_MASK \ | ||
743 | GENMASK(31, 24) | ||
744 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_SHIFT 24 | ||
745 | |||
746 | /* Voltage Policy Table */ | ||
747 | struct vbios_voltage_policy_table_1x_header { | ||
748 | u8 version; | ||
749 | u8 header_size; | ||
750 | u8 table_entry_size; | ||
751 | u8 num_table_entries; | ||
752 | u8 perf_core_vf_seq_policy_idx; | ||
753 | }; | ||
754 | |||
755 | struct vbios_voltage_policy_table_1x_entry { | ||
756 | u8 type; | ||
757 | u32 param0; | ||
758 | u32 param1; | ||
759 | }; | ||
760 | |||
761 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00 | ||
762 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01 | ||
763 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02 | ||
764 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03 | ||
765 | |||
766 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ | ||
767 | GENMASK(7, 0) | ||
768 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_SHIFT 0 | ||
769 | #define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_MASK GENMASK(8, 31) | ||
770 | #define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_SHIFT 8 | ||
771 | |||
772 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_MASK \ | ||
773 | GENMASK(7, 0) | ||
774 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_SHIFT 0 | ||
775 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_MASK \ | ||
776 | GENMASK(15, 8) | ||
777 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_SHIFT 8 | ||
778 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_MASK \ | ||
779 | GENMASK(23, 16) | ||
780 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_SHIFT 16 | ||
781 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_MASK \ | ||
782 | GENMASK(31, 24) | ||
783 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24 | ||
784 | |||
785 | /* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */ | ||
786 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ | ||
787 | GENMASK(15, 0) | ||
788 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \ | ||
789 | 0 | ||
790 | |||
791 | #define VBIOS_THERM_DEVICE_VERSION_1X 0x10 | ||
792 | |||
793 | #define VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04 0x00000004 | ||
794 | |||
795 | struct therm_device_1x_header { | ||
796 | u8 version; | ||
797 | u8 header_size; | ||
798 | u8 table_entry_size; | ||
799 | u8 num_table_entries; | ||
800 | } ; | ||
801 | |||
802 | struct therm_device_1x_entry { | ||
803 | u8 class_id; | ||
804 | u8 param0; | ||
805 | u8 flags; | ||
806 | } ; | ||
807 | |||
808 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU 0x01 | ||
809 | |||
810 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK 0xFF | ||
811 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT 0 | ||
812 | |||
813 | #define VBIOS_THERM_CHANNEL_VERSION_1X 0x10 | ||
814 | |||
815 | #define VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09 0x00000009 | ||
816 | |||
817 | struct therm_channel_1x_header { | ||
818 | u8 version; | ||
819 | u8 header_size; | ||
820 | u8 table_entry_size; | ||
821 | u8 num_table_entries; | ||
822 | u8 gpu_avg_pri_ch_idx; | ||
823 | u8 gpu_max_pri_ch_idx; | ||
824 | u8 board_pri_ch_idx; | ||
825 | u8 mem_pri_ch_idx; | ||
826 | u8 pwr_supply_pri_ch_idx; | ||
827 | }; | ||
828 | |||
829 | struct therm_channel_1x_entry { | ||
830 | u8 class_id; | ||
831 | u8 param0; | ||
832 | u8 param1; | ||
833 | u8 param2; | ||
834 | u8 flags; | ||
835 | }; | ||
836 | |||
837 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE 0x01 | ||
838 | |||
839 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_MASK 0xFF | ||
840 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_SHIFT 0 | ||
841 | |||
842 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_MASK 0xFF | ||
843 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_SHIFT 0 | ||
844 | |||
845 | /* Frequency Controller Table */ | ||
846 | struct vbios_fct_1x_header { | ||
847 | u8 version; | ||
848 | u8 header_size; | ||
849 | u8 entry_size; | ||
850 | u8 entry_count; | ||
851 | u16 sampling_period_ms; | ||
852 | } __packed; | ||
853 | |||
854 | struct vbios_fct_1x_entry { | ||
855 | u8 flags0; | ||
856 | u8 clk_domain_idx; | ||
857 | u16 param0; | ||
858 | u16 param1; | ||
859 | u32 param2; | ||
860 | u32 param3; | ||
861 | u32 param4; | ||
862 | u32 param5; | ||
863 | u32 param6; | ||
864 | u32 param7; | ||
865 | u32 param8; | ||
866 | } __packed; | ||
867 | |||
868 | #define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_MASK GENMASK(3, 0) | ||
869 | #define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 | ||
870 | #define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_DISABLED 0x0 | ||
871 | #define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_PI 0x1 | ||
872 | |||
873 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_MASK GENMASK(7, 0) | ||
874 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SHIFT 0 | ||
875 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SYS 0x00 | ||
876 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_LTC 0x01 | ||
877 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_XBAR 0x02 | ||
878 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC0 0x03 | ||
879 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC1 0x04 | ||
880 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC2 0x05 | ||
881 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC3 0x06 | ||
882 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC4 0x07 | ||
883 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC5 0x08 | ||
884 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPCS 0x09 | ||
885 | |||
886 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MASK GENMASK(9, 8) | ||
887 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_SHIFT 8 | ||
888 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_BCAST 0x0 | ||
889 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MIN 0x1 | ||
890 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MAX 0x2 | ||
891 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_AVG 0x3 | ||
892 | |||
893 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_MASK GENMASK(7, 0) | ||
894 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_SHIFT 0 | ||
895 | |||
896 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_MASK GENMASK(8, 8) | ||
897 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_SHIFT 8 | ||
898 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_NO 0x0 | ||
899 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_YES 0x1 | ||
900 | |||
901 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_MASK GENMASK(31, 0) | ||
902 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_SHIFT 0 | ||
903 | |||
904 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_MASK GENMASK(31, 0) | ||
905 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_SHIFT 0 | ||
906 | |||
907 | |||
908 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_MASK GENMASK(31, 0) | ||
909 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_SHIFT 0 | ||
910 | |||
911 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_MASK GENMASK(31, 0) | ||
912 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_SHIFT 0 | ||
913 | |||
914 | |||
915 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_MASK GENMASK(31, 0) | ||
916 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_SHIFT 0 | ||
917 | |||
918 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_MASK GENMASK(15, 0) | ||
919 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_SHIFT 0 | ||
920 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_MASK GENMASK(31, 16) | ||
921 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_SHIFT 16 | ||
922 | |||
923 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_MASK GENMASK(15, 0) | ||
924 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_SHIFT 0 | ||
925 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_MASK GENMASK(31, 16) | ||
926 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_SHIFT 16 | ||
927 | |||
928 | /* LPWR Index Table */ | ||
929 | struct nvgpu_bios_lpwr_idx_table_1x_header { | ||
930 | u8 version; | ||
931 | u8 header_size; | ||
932 | u8 entry_size; | ||
933 | u8 entry_count; | ||
934 | u16 base_sampling_period; | ||
935 | } __packed; | ||
936 | |||
937 | struct nvgpu_bios_lpwr_idx_table_1x_entry { | ||
938 | u8 pcie_idx; | ||
939 | u8 gr_idx; | ||
940 | u8 ms_idx; | ||
941 | u8 di_idx; | ||
942 | u8 gc6_idx; | ||
943 | } __packed; | ||
944 | |||
945 | /* LPWR MS Table*/ | ||
946 | struct nvgpu_bios_lpwr_ms_table_1x_header { | ||
947 | u8 version; | ||
948 | u8 header_size; | ||
949 | u8 entry_size; | ||
950 | u8 entry_count; | ||
951 | u8 default_entry_idx; | ||
952 | u16 idle_threshold_us; | ||
953 | } __packed; | ||
954 | |||
955 | struct nvgpu_bios_lpwr_ms_table_1x_entry { | ||
956 | u32 feautre_mask; | ||
957 | u16 dynamic_current_logic; | ||
958 | u16 dynamic_current_sram; | ||
959 | } __packed; | ||
960 | |||
961 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_MASK GENMASK(0, 0) | ||
962 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SHIFT 0 | ||
963 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_MASK GENMASK(2, 2) | ||
964 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_SHIFT 2 | ||
965 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_MASK \ | ||
966 | GENMASK(3, 3) | ||
967 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_SHIFT 3 | ||
968 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_MASK GENMASK(5, 5) | ||
969 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_SHIFT 5 | ||
970 | |||
971 | /* LPWR GR Table */ | ||
972 | struct nvgpu_bios_lpwr_gr_table_1x_header { | ||
973 | u8 version; | ||
974 | u8 header_size; | ||
975 | u8 entry_size; | ||
976 | u8 entry_count; | ||
977 | u8 default_entry_idx; | ||
978 | u16 idle_threshold_us; | ||
979 | u8 adaptive_gr_multiplier; | ||
980 | } __packed; | ||
981 | |||
982 | struct nvgpu_bios_lpwr_gr_table_1x_entry { | ||
983 | u32 feautre_mask; | ||
984 | } __packed; | ||
985 | |||
986 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_MASK GENMASK(0, 0) | ||
987 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_SHIFT 0 | ||
988 | |||
989 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4) | ||
990 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4 | ||
991 | |||
992 | #endif | ||