1 files changed, 132 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/bios.h
index d3a677f8..fb1e1f46 100644
--- a/drivers/gpu/nvgpu/include/bios.h
+++ b/drivers/gpu/nvgpu/include/bios.h
@@ -656,4 +656,136 @@ struct pwr_policy_3x_entry_struct {
 #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF
 #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0
 
+/* Voltage Rail Table */
+struct vbios_voltage_rail_table_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 table_entry_size;
+        u8 num_table_entries;
+        u8 volt_domain_hal;
+} __packed;
+
+#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07          0X00000007
+#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08          0X00000008
+#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09          0X00000009
+#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A          0X0000000A
+#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B          0X0000000B
+
+struct vbios_voltage_rail_table_1x_entry {
+        u32 boot_voltage_uv;
+        u8 rel_limit_vfe_equ_idx;
+        u8 alt_rel_limit_vfe_equidx;
+        u8 ov_limit_vfe_equ_idx;
+        u8 pwr_equ_idx;
+        u8 boot_volt_vfe_equ_idx;
+        u8 vmin_limit_vfe_equ_idx;
+        u8 volt_margin_limit_vfe_equ_idx;
+} __packed;
+
+/* Voltage Device Table */
+struct vbios_voltage_device_table_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 table_entry_size;
+        u8 num_table_entries;
+};
+
+struct vbios_voltage_device_table_1x_entry {
+        u8 type;
+        u8 volt_domain;
+        u16 settle_time_us;
+        u32 param0;
+        u32 param1;
+        u32 param2;
+        u32 param3;
+        u32 param4;
+};
+
+#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID   0x00
+#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV               0x02
+
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK   \
+                GENMASK(23, 0)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_SHIFT  0
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_MASK  \
+        GENMASK(31, 24)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_SHIFT 24
+
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_MASK   \
+                GENMASK(23, 0)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_SHIFT  0
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_MASK    \
+        GENMASK(31, 24)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_SHIFT           24
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT 0x00
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE \
+                0x01
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE \
+                0x02
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_MASK   \
+                GENMASK(23, 0)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_SHIFT  0
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_MASK              \
+                GENMASK(31, 24)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_SHIFT             24
+
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_MASK      \
+                GENMASK(23, 0)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_SHIFT     0
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_MASK     \
+                GENMASK(31, 24)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_SHIFT    24
+
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_MASK \
+                GENMASK(23, 0)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_SHIFT     0
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_MASK              \
+                GENMASK(31, 24)
+#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_SHIFT     24
+
+/* Voltage Policy Table */
+struct vbios_voltage_policy_table_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 table_entry_size;
+        u8 num_table_entries;
+        u8 perf_core_vf_seq_policy_idx;
+};
+
+struct vbios_voltage_policy_table_1x_entry {
+        u8 type;
+        u32 param0;
+        u32 param1;
+};
+
+#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID           0x00
+#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL       0x01
+#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP     0x02
+#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP    0x03
+
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \
+                GENMASK(7, 0)
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_SHIFT 0
+#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_MASK     GENMASK(8, 31)
+#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_SHIFT    8
+
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_MASK \
+                GENMASK(7, 0)
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_SHIFT 0
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_MASK \
+                GENMASK(15, 8)
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_SHIFT 8
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_MASK \
+                GENMASK(23, 16)
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_SHIFT 16
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_MASK \
+                GENMASK(31, 24)
+#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24
+
+/* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */
+#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \
+                GENMASK(15, 0)
+#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \
+                0
+
 #endif