diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 35 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 |
3 files changed, 39 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 1d5e593c..b4e4b875 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -1811,3 +1811,38 @@ void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, | |||
1811 | else | 1811 | else |
1812 | *pbdma_id = FIFO_INVAL_PBDMA_ID; | 1812 | *pbdma_id = FIFO_INVAL_PBDMA_ID; |
1813 | } | 1813 | } |
1814 | |||
1815 | static bool gk20a_fifo_channel_status_is_eng_faulted(struct gk20a *g, u32 chid) | ||
1816 | { | ||
1817 | u32 channel = gk20a_readl(g, ccsr_channel_r(chid)); | ||
1818 | |||
1819 | return ccsr_channel_eng_faulted_v(channel) == | ||
1820 | ccsr_channel_eng_faulted_true_v(); | ||
1821 | } | ||
1822 | |||
1823 | void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch) | ||
1824 | { | ||
1825 | struct gk20a *g = ch->g; | ||
1826 | struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; | ||
1827 | |||
1828 | /* | ||
1829 | * If channel has FAULTED set, clear the CE method buffer | ||
1830 | * if saved out channel is same as faulted channel | ||
1831 | */ | ||
1832 | if (!gk20a_fifo_channel_status_is_eng_faulted(g, ch->chid)) | ||
1833 | return; | ||
1834 | |||
1835 | if (tsg->eng_method_buffers == NULL) | ||
1836 | return; | ||
1837 | |||
1838 | /* | ||
1839 | * CE method buffer format : | ||
1840 | * DWord0 = method count | ||
1841 | * DWord1 = channel id | ||
1842 | * | ||
1843 | * It is sufficient to write 0 to method count to invalidate | ||
1844 | */ | ||
1845 | if ((u32)ch->chid == | ||
1846 | nvgpu_mem_rd32(g, &tsg->eng_method_buffers[ASYNC_CE_RUNQUE], 1)) | ||
1847 | nvgpu_mem_wr32(g, &tsg->eng_method_buffers[ASYNC_CE_RUNQUE], 0, 0); | ||
1848 | } | ||
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index e576714c..0cc1c7c2 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | |||
@@ -103,4 +103,6 @@ void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, | |||
103 | u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd); | 103 | u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd); |
104 | int gv11b_init_fifo_setup_hw(struct gk20a *g); | 104 | int gv11b_init_fifo_setup_hw(struct gk20a *g); |
105 | 105 | ||
106 | void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch); | ||
107 | |||
106 | #endif | 108 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 947ac503..fcc3b91a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -432,6 +432,8 @@ static const struct gpu_ops gv11b_ops = { | |||
432 | .preempt_tsg = gv11b_fifo_preempt_tsg, | 432 | .preempt_tsg = gv11b_fifo_preempt_tsg, |
433 | .enable_tsg = gv11b_fifo_enable_tsg, | 433 | .enable_tsg = gv11b_fifo_enable_tsg, |
434 | .disable_tsg = gk20a_disable_tsg, | 434 | .disable_tsg = gk20a_disable_tsg, |
435 | .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, | ||
436 | .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, | ||
435 | .update_runlist = gk20a_fifo_update_runlist, | 437 | .update_runlist = gk20a_fifo_update_runlist, |
436 | .trigger_mmu_fault = NULL, | 438 | .trigger_mmu_fault = NULL, |
437 | .get_mmu_fault_info = NULL, | 439 | .get_mmu_fault_info = NULL, |