diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 109 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 4 |
2 files changed, 68 insertions, 45 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 1e001824..bc659a7b 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -3212,18 +3212,42 @@ void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state) | |||
3212 | } | 3212 | } |
3213 | } | 3213 | } |
3214 | 3214 | ||
3215 | static void gv11b_gr_write_sm_error_state(struct gk20a *g, | ||
3216 | u32 offset, | ||
3217 | struct nvgpu_tsg_sm_error_state *sm_error_states) | ||
3218 | { | ||
3219 | nvgpu_writel(g, | ||
3220 | gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, | ||
3221 | sm_error_states->hww_global_esr); | ||
3222 | nvgpu_writel(g, | ||
3223 | gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset, | ||
3224 | sm_error_states->hww_warp_esr); | ||
3225 | nvgpu_writel(g, | ||
3226 | gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() + offset, | ||
3227 | u64_lo32(sm_error_states->hww_warp_esr_pc)); | ||
3228 | nvgpu_writel(g, | ||
3229 | gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r() + offset, | ||
3230 | u64_hi32(sm_error_states->hww_warp_esr_pc)); | ||
3231 | nvgpu_writel(g, | ||
3232 | gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset, | ||
3233 | sm_error_states->hww_global_esr_report_mask); | ||
3234 | nvgpu_writel(g, | ||
3235 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset, | ||
3236 | sm_error_states->hww_warp_esr_report_mask); | ||
3237 | } | ||
3238 | |||
3215 | int gv11b_gr_update_sm_error_state(struct gk20a *g, | 3239 | int gv11b_gr_update_sm_error_state(struct gk20a *g, |
3216 | struct channel_gk20a *ch, u32 sm_id, | 3240 | struct channel_gk20a *ch, u32 sm_id, |
3217 | struct nvgpu_gr_sm_error_state *sm_error_state) | 3241 | struct nvgpu_tsg_sm_error_state *sm_error_state) |
3218 | { | 3242 | { |
3219 | struct tsg_gk20a *tsg; | 3243 | struct tsg_gk20a *tsg; |
3220 | u32 gpc, tpc, sm, offset; | 3244 | u32 gpc, tpc, sm, offset; |
3221 | struct gr_gk20a *gr = &g->gr; | ||
3222 | struct nvgpu_gr_ctx *ch_ctx; | 3245 | struct nvgpu_gr_ctx *ch_ctx; |
3223 | int err = 0; | 3246 | int err = 0; |
3247 | struct nvgpu_tsg_sm_error_state *tsg_sm_error_states; | ||
3224 | 3248 | ||
3225 | tsg = tsg_gk20a_from_ch(ch); | 3249 | tsg = tsg_gk20a_from_ch(ch); |
3226 | if (!tsg) { | 3250 | if (tsg == NULL) { |
3227 | return -EINVAL; | 3251 | return -EINVAL; |
3228 | } | 3252 | } |
3229 | 3253 | ||
@@ -3231,16 +3255,8 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g, | |||
3231 | 3255 | ||
3232 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 3256 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
3233 | 3257 | ||
3234 | gr->sm_error_states[sm_id].hww_global_esr = | 3258 | tsg_sm_error_states = tsg->sm_error_states + sm_id; |
3235 | sm_error_state->hww_global_esr; | 3259 | gk20a_tsg_update_sm_error_state_locked(tsg, sm_id, sm_error_state); |
3236 | gr->sm_error_states[sm_id].hww_warp_esr = | ||
3237 | sm_error_state->hww_warp_esr; | ||
3238 | gr->sm_error_states[sm_id].hww_warp_esr_pc = | ||
3239 | sm_error_state->hww_warp_esr_pc; | ||
3240 | gr->sm_error_states[sm_id].hww_global_esr_report_mask = | ||
3241 | sm_error_state->hww_global_esr_report_mask; | ||
3242 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask = | ||
3243 | sm_error_state->hww_warp_esr_report_mask; | ||
3244 | 3260 | ||
3245 | err = gr_gk20a_disable_ctxsw(g); | 3261 | err = gr_gk20a_disable_ctxsw(g); |
3246 | if (err) { | 3262 | if (err) { |
@@ -3257,21 +3273,7 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g, | |||
3257 | gv11b_gr_sm_offset(g, sm); | 3273 | gv11b_gr_sm_offset(g, sm); |
3258 | 3274 | ||
3259 | if (gk20a_is_channel_ctx_resident(ch)) { | 3275 | if (gk20a_is_channel_ctx_resident(ch)) { |
3260 | gk20a_writel(g, | 3276 | gv11b_gr_write_sm_error_state(g, offset, tsg_sm_error_states); |
3261 | gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, | ||
3262 | gr->sm_error_states[sm_id].hww_global_esr); | ||
3263 | gk20a_writel(g, | ||
3264 | gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset, | ||
3265 | gr->sm_error_states[sm_id].hww_warp_esr); | ||
3266 | gk20a_writel(g, | ||
3267 | gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() + offset, | ||
3268 | gr->sm_error_states[sm_id].hww_warp_esr_pc); | ||
3269 | gk20a_writel(g, | ||
3270 | gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset, | ||
3271 | gr->sm_error_states[sm_id].hww_global_esr_report_mask); | ||
3272 | gk20a_writel(g, | ||
3273 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset, | ||
3274 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask); | ||
3275 | } else { | 3277 | } else { |
3276 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false); | 3278 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false); |
3277 | if (err) { | 3279 | if (err) { |
@@ -3281,12 +3283,12 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g, | |||
3281 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 3283 | gr_gk20a_ctx_patch_write(g, ch_ctx, |
3282 | gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() + | 3284 | gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() + |
3283 | offset, | 3285 | offset, |
3284 | gr->sm_error_states[sm_id].hww_global_esr_report_mask, | 3286 | tsg_sm_error_states->hww_global_esr_report_mask, |
3285 | true); | 3287 | true); |
3286 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 3288 | gr_gk20a_ctx_patch_write(g, ch_ctx, |
3287 | gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() + | 3289 | gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() + |
3288 | offset, | 3290 | offset, |
3289 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask, | 3291 | tsg_sm_error_states->hww_warp_esr_report_mask, |
3290 | true); | 3292 | true); |
3291 | 3293 | ||
3292 | gr_gk20a_ctx_patch_write_end(g, ch_ctx, false); | 3294 | gr_gk20a_ctx_patch_write_end(g, ch_ctx, false); |
@@ -3362,13 +3364,36 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | |||
3362 | return err; | 3364 | return err; |
3363 | } | 3365 | } |
3364 | 3366 | ||
3367 | static void gv11b_gr_read_sm_error_state(struct gk20a *g, | ||
3368 | u32 offset, | ||
3369 | struct nvgpu_tsg_sm_error_state *sm_error_states) | ||
3370 | { | ||
3371 | sm_error_states->hww_global_esr = nvgpu_readl(g, | ||
3372 | gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset); | ||
3373 | |||
3374 | sm_error_states->hww_warp_esr = nvgpu_readl(g, | ||
3375 | gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset); | ||
3376 | |||
3377 | sm_error_states->hww_warp_esr_pc = hi32_lo32_to_u64((nvgpu_readl(g, | ||
3378 | gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r() + offset)), | ||
3379 | (nvgpu_readl(g, | ||
3380 | gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() + offset))); | ||
3381 | |||
3382 | sm_error_states->hww_global_esr_report_mask = nvgpu_readl(g, | ||
3383 | gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset); | ||
3384 | |||
3385 | sm_error_states->hww_warp_esr_report_mask = nvgpu_readl(g, | ||
3386 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset); | ||
3387 | } | ||
3388 | |||
3365 | int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 3389 | int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
3366 | struct channel_gk20a *fault_ch) | 3390 | struct channel_gk20a *fault_ch) |
3367 | { | 3391 | { |
3368 | int sm_id; | 3392 | int sm_id; |
3369 | struct gr_gk20a *gr = &g->gr; | ||
3370 | u32 offset, sm_per_tpc, tpc_id; | 3393 | u32 offset, sm_per_tpc, tpc_id; |
3371 | u32 gpc_offset, gpc_tpc_offset; | 3394 | u32 gpc_offset, gpc_tpc_offset; |
3395 | struct nvgpu_tsg_sm_error_state *sm_error_states = NULL; | ||
3396 | struct tsg_gk20a *tsg = NULL; | ||
3372 | 3397 | ||
3373 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 3398 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
3374 | 3399 | ||
@@ -3381,21 +3406,19 @@ int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | |||
3381 | 3406 | ||
3382 | offset = gpc_tpc_offset + gv11b_gr_sm_offset(g, sm); | 3407 | offset = gpc_tpc_offset + gv11b_gr_sm_offset(g, sm); |
3383 | 3408 | ||
3384 | gr->sm_error_states[sm_id].hww_global_esr = gk20a_readl(g, | 3409 | if (fault_ch != NULL) { |
3385 | gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset); | 3410 | tsg = tsg_gk20a_from_ch(fault_ch); |
3386 | 3411 | } | |
3387 | gr->sm_error_states[sm_id].hww_warp_esr = gk20a_readl(g, | ||
3388 | gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset); | ||
3389 | |||
3390 | gr->sm_error_states[sm_id].hww_warp_esr_pc = gk20a_readl(g, | ||
3391 | gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() + offset); | ||
3392 | 3412 | ||
3393 | gr->sm_error_states[sm_id].hww_global_esr_report_mask = gk20a_readl(g, | 3413 | if (tsg == NULL) { |
3394 | gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset); | 3414 | nvgpu_err(g, "no valid tsg"); |
3415 | goto record_fail; | ||
3416 | } | ||
3395 | 3417 | ||
3396 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask = gk20a_readl(g, | 3418 | sm_error_states = tsg->sm_error_states + sm_id; |
3397 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset); | 3419 | gv11b_gr_read_sm_error_state(g, offset, sm_error_states); |
3398 | 3420 | ||
3421 | record_fail: | ||
3399 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 3422 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
3400 | 3423 | ||
3401 | return sm_id; | 3424 | return sm_id; |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 0f29ea24..30cc7f0a 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -43,7 +43,7 @@ struct zbc_entry; | |||
43 | struct zbc_query_params; | 43 | struct zbc_query_params; |
44 | struct nvgpu_gr_ctx; | 44 | struct nvgpu_gr_ctx; |
45 | struct nvgpu_warpstate; | 45 | struct nvgpu_warpstate; |
46 | struct nvgpu_gr_sm_error_state; | 46 | struct nvgpu_tsg_sm_error_state; |
47 | struct gr_ctx_desc; | 47 | struct gr_ctx_desc; |
48 | struct gr_gk20a_isr_data; | 48 | struct gr_gk20a_isr_data; |
49 | struct gk20a_debug_output; | 49 | struct gk20a_debug_output; |
@@ -168,7 +168,7 @@ int gv11b_gr_sm_trigger_suspend(struct gk20a *g); | |||
168 | void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); | 168 | void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); |
169 | int gv11b_gr_update_sm_error_state(struct gk20a *g, | 169 | int gv11b_gr_update_sm_error_state(struct gk20a *g, |
170 | struct channel_gk20a *ch, u32 sm_id, | 170 | struct channel_gk20a *ch, u32 sm_id, |
171 | struct nvgpu_gr_sm_error_state *sm_error_state); | 171 | struct nvgpu_tsg_sm_error_state *sm_error_state); |
172 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | 172 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, |
173 | struct channel_gk20a *ch, u64 sms, bool enable); | 173 | struct channel_gk20a *ch, u64 sms, bool enable); |
174 | int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 174 | int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |