3 files changed, 107 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 6b4eeb88..2225e380 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -88,6 +88,7 @@
 #include "regops_gv11b.h"
 #include "subctx_gv11b.h"
 #include "ecc_gv11b.h"
+#include "tpc_gv11b.h"
 
 #include <nvgpu/ptimer.h>
 #include <nvgpu/debug.h>
@@ -859,6 +860,9 @@ static const struct gpu_ops gv11b_ops = {
         .acr = {
                 .acr_sw_init = nvgpu_gv11b_acr_sw_init,
         },
+        .tpc = {
+                .tpc_powergate = gv11b_tpc_powergate,
+        },
         .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics,
         .get_litter_value = gv11b_get_litter_value,
 };
@@ -893,6 +897,7 @@ int gv11b_init_hal(struct gk20a *g)
         gops->falcon = gv11b_ops.falcon;
         gops->priv_ring = gv11b_ops.priv_ring;
         gops->fuse = gv11b_ops.fuse;
+        gops->tpc = gv11b_ops.tpc;
         gops->clk_arb = gv11b_ops.clk_arb;
         gops->acr = gv11b_ops.acr;
 
diff --git a/drivers/gpu/nvgpu/gv11b/tpc_gv11b.c b/drivers/gpu/nvgpu/gv11b/tpc_gv11b.c
new file mode 100644
index 00000000..3177870c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv11b/tpc_gv11b.c
@@ -0,0 +1,70 @@
+/*
+ * GV11B TPC
+ *
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include <nvgpu/gk20a.h>
+#include "tpc_gv11b.h"
+
+int gv11b_tpc_powergate(struct gk20a *g, u32 fuse_status)
+{
+        int err = 0;
+
+        if (fuse_status == 0x0) {
+                g->can_tpc_powergate = true;
+
+        } else {
+                /* if hardware has already floorswept any TPC
+                 * (fuse_status !=  0x0) and if TPC PG mask
+                 * sent from userspace is 0x0 GPU will be powered on
+                 * with the default fuse_status setting. It cannot
+                 * un-floorsweep any TPC
+                 * thus, set g->tpc_pg_mask to fuse_status value
+                 */
+                if (g->tpc_pg_mask == 0x0) {
+                        g->can_tpc_powergate = true;
+                        g->tpc_pg_mask = fuse_status;
+
+                } else if (fuse_status == g->tpc_pg_mask) {
+                        g->can_tpc_powergate = true;
+
+                } else if ((fuse_status & g->tpc_pg_mask) ==
+                                        fuse_status) {
+                        g->can_tpc_powergate = true;
+
+                } else {
+                        /* If userspace sends a TPC PG mask such that
+                         * it tries to un-floorsweep any TPC which is
+                         * already powergated from hardware, then
+                         * such mask is invalid.
+                         * In this case set tpc pg mask to 0x0
+                         * Return -EINVAL here and halt GPU poweron.
+                         */
+                        nvgpu_err(g, "Invalid TPC_PG mask: 0x%x",
+                                                        g->tpc_pg_mask);
+                        g->can_tpc_powergate = false;
+                        g->tpc_pg_mask = 0x0;
+                        err = -EINVAL;
+                }
+        }
+
+        return err;
+}
diff --git a/drivers/gpu/nvgpu/gv11b/tpc_gv11b.h b/drivers/gpu/nvgpu/gv11b/tpc_gv11b.h
new file mode 100644
index 00000000..e860c22d
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv11b/tpc_gv11b.h
@@ -0,0 +1,32 @@
+/*
+ * GV11B TPC
+ *
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_TPC_GV11B_H
+#define NVGPU_TPC_GV11B_H
+
+struct gk20a;
+
+int gv11b_tpc_powergate(struct gk20a *g, u32 fuse_status);
+
+#endif /* NVGPU_TPC_GV11B_H */