diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fb_gv11b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 16 |
2 files changed, 15 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h index d9a6fa77..0b8f9fbf 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B FB | 2 | * GV11B FB |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -37,11 +37,11 @@ | |||
37 | #define FAULT_BUF_INVALID 0 | 37 | #define FAULT_BUF_INVALID 0 |
38 | #define FAULT_BUF_VALID 1 | 38 | #define FAULT_BUF_VALID 1 |
39 | 39 | ||
40 | #define HUB_INTR_TYPE_OTHER 1 /* bit 0 */ | 40 | #define HUB_INTR_TYPE_OTHER 1U /* bit 0 */ |
41 | #define HUB_INTR_TYPE_NONREPLAY 2 /* bit 1 */ | 41 | #define HUB_INTR_TYPE_NONREPLAY 2U /* bit 1 */ |
42 | #define HUB_INTR_TYPE_REPLAY 4 /* bit 2 */ | 42 | #define HUB_INTR_TYPE_REPLAY 4U /* bit 2 */ |
43 | #define HUB_INTR_TYPE_ECC_UNCORRECTED 8 /* bit 3 */ | 43 | #define HUB_INTR_TYPE_ECC_UNCORRECTED 8U /* bit 3 */ |
44 | #define HUB_INTR_TYPE_ACCESS_COUNTER 16 /* bit 4 */ | 44 | #define HUB_INTR_TYPE_ACCESS_COUNTER 16U /* bit 4 */ |
45 | #define HUB_INTR_TYPE_ALL (HUB_INTR_TYPE_OTHER | \ | 45 | #define HUB_INTR_TYPE_ALL (HUB_INTR_TYPE_OTHER | \ |
46 | HUB_INTR_TYPE_NONREPLAY | \ | 46 | HUB_INTR_TYPE_NONREPLAY | \ |
47 | HUB_INTR_TYPE_REPLAY | \ | 47 | HUB_INTR_TYPE_REPLAY | \ |
diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 74c5c4d6..6c118ceb 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B master | 2 | * GV11B master |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -22,7 +22,7 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <linux/types.h> | 25 | #include <nvgpu/types.h> |
26 | 26 | ||
27 | #include "gk20a/gk20a.h" | 27 | #include "gk20a/gk20a.h" |
28 | 28 | ||
@@ -38,9 +38,9 @@ void mc_gv11b_intr_enable(struct gk20a *g) | |||
38 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | 38 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); |
39 | 39 | ||
40 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), | 40 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), |
41 | 0xffffffff); | 41 | 0xffffffffU); |
42 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), | 42 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), |
43 | 0xffffffff); | 43 | 0xffffffffU); |
44 | gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); | 44 | gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); |
45 | 45 | ||
46 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = | 46 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = |
@@ -68,7 +68,7 @@ void mc_gv11b_intr_enable(struct gk20a *g) | |||
68 | 68 | ||
69 | bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) | 69 | bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) |
70 | { | 70 | { |
71 | return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false); | 71 | return (((mc_intr_0 & mc_intr_hub_pending_f()) != 0U) ? true : false); |
72 | } | 72 | } |
73 | 73 | ||
74 | bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id) | 74 | bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id) |
@@ -77,16 +77,18 @@ bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id) | |||
77 | u32 stall_intr, eng_intr_mask; | 77 | u32 stall_intr, eng_intr_mask; |
78 | 78 | ||
79 | eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); | 79 | eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); |
80 | if (mc_intr_0 & eng_intr_mask) | 80 | if ((mc_intr_0 & eng_intr_mask) != 0U) { |
81 | return true; | 81 | return true; |
82 | } | ||
82 | 83 | ||
83 | stall_intr = mc_intr_pfifo_pending_f() | | 84 | stall_intr = mc_intr_pfifo_pending_f() | |
84 | mc_intr_hub_pending_f() | | 85 | mc_intr_hub_pending_f() | |
85 | mc_intr_priv_ring_pending_f() | | 86 | mc_intr_priv_ring_pending_f() | |
86 | mc_intr_pbus_pending_f() | | 87 | mc_intr_pbus_pending_f() | |
87 | mc_intr_ltc_pending_f(); | 88 | mc_intr_ltc_pending_f(); |
88 | if (mc_intr_0 & stall_intr) | 89 | if ((mc_intr_0 & stall_intr) != 0U) { |
89 | return true; | 90 | return true; |
91 | } | ||
90 | 92 | ||
91 | return false; | 93 | return false; |
92 | } | 94 | } |