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-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c36
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.h1
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c8
-rw-r--r--drivers/gpu/nvgpu/gv11b/therm_gv11b.c148
-rw-r--r--drivers/gpu/nvgpu/gv11b/therm_gv11b.h29
5 files changed, 5 insertions, 217 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 058a21e5..c2cf909a 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -58,7 +58,6 @@
58#include <nvgpu/hw/gv11b/hw_mc_gv11b.h> 58#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
59#include <nvgpu/hw/gv11b/hw_ram_gv11b.h> 59#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
60#include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> 60#include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
61#include <nvgpu/hw/gv11b/hw_therm_gv11b.h>
62#include <nvgpu/hw/gv11b/hw_perf_gv11b.h> 61#include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
63#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h> 62#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
64 63
@@ -2915,41 +2914,6 @@ void gr_gv11b_write_pm_ptr(struct gk20a *g,
2915 ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); 2914 ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi);
2916} 2915}
2917 2916
2918void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
2919{
2920 u32 gate_ctrl;
2921
2922 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG))
2923 return;
2924
2925 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
2926
2927 switch (mode) {
2928 case ELCG_RUN:
2929 gate_ctrl = set_field(gate_ctrl,
2930 therm_gate_ctrl_eng_clk_m(),
2931 therm_gate_ctrl_eng_clk_run_f());
2932 gate_ctrl = set_field(gate_ctrl,
2933 therm_gate_ctrl_idle_holdoff_m(),
2934 therm_gate_ctrl_idle_holdoff_on_f());
2935 break;
2936 case ELCG_STOP:
2937 gate_ctrl = set_field(gate_ctrl,
2938 therm_gate_ctrl_eng_clk_m(),
2939 therm_gate_ctrl_eng_clk_stop_f());
2940 break;
2941 case ELCG_AUTO:
2942 gate_ctrl = set_field(gate_ctrl,
2943 therm_gate_ctrl_eng_clk_m(),
2944 therm_gate_ctrl_eng_clk_auto_f());
2945 break;
2946 default:
2947 nvgpu_err(g, "invalid elcg mode %d", mode);
2948 }
2949
2950 gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
2951}
2952
2953void gr_gv11b_load_tpc_mask(struct gk20a *g) 2917void gr_gv11b_load_tpc_mask(struct gk20a *g)
2954{ 2918{
2955 u32 pes_tpc_mask = 0, fuse_tpc_mask; 2919 u32 pes_tpc_mask = 0, fuse_tpc_mask;
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 0a8a536c..0f29ea24 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -158,7 +158,6 @@ void gr_gv11b_write_zcull_ptr(struct gk20a *g,
158 struct nvgpu_mem *mem, u64 gpu_va); 158 struct nvgpu_mem *mem, u64 gpu_va);
159void gr_gv11b_write_pm_ptr(struct gk20a *g, 159void gr_gv11b_write_pm_ptr(struct gk20a *g,
160 struct nvgpu_mem *mem, u64 gpu_va); 160 struct nvgpu_mem *mem, u64 gpu_va);
161void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine);
162void gr_gv11b_load_tpc_mask(struct gk20a *g); 161void gr_gv11b_load_tpc_mask(struct gk20a *g);
163void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, 162void gr_gv11b_set_preemption_buffer_va(struct gk20a *g,
164 struct nvgpu_mem *mem, u64 gpu_va); 163 struct nvgpu_mem *mem, u64 gpu_va);
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 05763cce..111a1ea2 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -33,6 +33,9 @@
33#include "common/fb/fb_gm20b.h" 33#include "common/fb/fb_gm20b.h"
34#include "common/fb/fb_gp10b.h" 34#include "common/fb/fb_gp10b.h"
35#include "common/fb/fb_gv11b.h" 35#include "common/fb/fb_gv11b.h"
36#include "common/therm/therm_gm20b.h"
37#include "common/therm/therm_gp10b.h"
38#include "common/therm/therm_gv11b.h"
36 39
37#include "gk20a/gk20a.h" 40#include "gk20a/gk20a.h"
38#include "gk20a/fifo_gk20a.h" 41#include "gk20a/fifo_gk20a.h"
@@ -54,7 +57,6 @@
54#include "gm20b/pmu_gm20b.h" 57#include "gm20b/pmu_gm20b.h"
55 58
56#include "gp10b/ltc_gp10b.h" 59#include "gp10b/ltc_gp10b.h"
57#include "gp10b/therm_gp10b.h"
58#include "gp10b/mc_gp10b.h" 60#include "gp10b/mc_gp10b.h"
59#include "gp10b/ce_gp10b.h" 61#include "gp10b/ce_gp10b.h"
60#include "gp10b/fifo_gp10b.h" 62#include "gp10b/fifo_gp10b.h"
@@ -84,7 +86,6 @@
84#include "fifo_gv11b.h" 86#include "fifo_gv11b.h"
85#include "regops_gv11b.h" 87#include "regops_gv11b.h"
86#include "subctx_gv11b.h" 88#include "subctx_gv11b.h"
87#include "therm_gv11b.h"
88#include "ecc_gv11b.h" 89#include "ecc_gv11b.h"
89 90
90#include <nvgpu/ptimer.h> 91#include <nvgpu/ptimer.h>
@@ -341,7 +342,6 @@ static const struct gpu_ops gv11b_ops = {
341 .commit_inst = gr_gv11b_commit_inst, 342 .commit_inst = gr_gv11b_commit_inst,
342 .write_zcull_ptr = gr_gv11b_write_zcull_ptr, 343 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
343 .write_pm_ptr = gr_gv11b_write_pm_ptr, 344 .write_pm_ptr = gr_gv11b_write_pm_ptr,
344 .init_elcg_mode = gr_gv11b_init_elcg_mode,
345 .load_tpc_mask = gr_gv11b_load_tpc_mask, 345 .load_tpc_mask = gr_gv11b_load_tpc_mask,
346 .inval_icache = gr_gk20a_inval_icache, 346 .inval_icache = gr_gk20a_inval_icache,
347 .trigger_suspend = gv11b_gr_sm_trigger_suspend, 347 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
@@ -664,6 +664,8 @@ static const struct gpu_ops gv11b_ops = {
664 }, 664 },
665 .therm = { 665 .therm = {
666 .init_therm_setup_hw = gv11b_init_therm_setup_hw, 666 .init_therm_setup_hw = gv11b_init_therm_setup_hw,
667 .init_elcg_mode = gv11b_therm_init_elcg_mode,
668 .init_blcg_mode = gm20b_therm_init_blcg_mode,
667 .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, 669 .elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
668 }, 670 },
669 .pmu = { 671 .pmu = {
diff --git a/drivers/gpu/nvgpu/gv11b/therm_gv11b.c b/drivers/gpu/nvgpu/gv11b/therm_gv11b.c
deleted file mode 100644
index acc2c509..00000000
--- a/drivers/gpu/nvgpu/gv11b/therm_gv11b.c
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * GV11B Therm
3 *
4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "gk20a/gk20a.h"
26#include "therm_gv11b.h"
27
28#include <nvgpu/soc.h>
29#include <nvgpu/io.h>
30#include <nvgpu/utils.h>
31
32#include <nvgpu/hw/gv11b/hw_therm_gv11b.h>
33
34#include "therm_gv11b.h"
35
36int gv11b_init_therm_setup_hw(struct gk20a *g)
37{
38 u32 v;
39
40 nvgpu_log_fn(g, " ");
41
42 /* program NV_THERM registers */
43 gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() |
44 therm_use_a_ext_therm_1_enable_f() |
45 therm_use_a_ext_therm_2_enable_f());
46 gk20a_writel(g, therm_evt_ext_therm_0_r(),
47 therm_evt_ext_therm_0_slow_factor_f(0x2));
48 gk20a_writel(g, therm_evt_ext_therm_1_r(),
49 therm_evt_ext_therm_1_slow_factor_f(0x6));
50 gk20a_writel(g, therm_evt_ext_therm_2_r(),
51 therm_evt_ext_therm_2_slow_factor_f(0xe));
52
53 gk20a_writel(g, therm_grad_stepping_table_r(0),
54 therm_grad_stepping_table_slowdown_factor0_f(
55 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1_f()) |
56 therm_grad_stepping_table_slowdown_factor1_f(
57 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) |
58 therm_grad_stepping_table_slowdown_factor2_f(
59 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) |
60 therm_grad_stepping_table_slowdown_factor3_f(
61 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) |
62 therm_grad_stepping_table_slowdown_factor4_f(
63 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
64
65 gk20a_writel(g, therm_grad_stepping_table_r(1),
66 therm_grad_stepping_table_slowdown_factor0_f(
67 therm_grad_stepping_table_slowdown_factor0_fpdiv_by16_f()) |
68 therm_grad_stepping_table_slowdown_factor1_f(
69 therm_grad_stepping_table_slowdown_factor0_fpdiv_by32_f()) |
70 therm_grad_stepping_table_slowdown_factor2_f(
71 therm_grad_stepping_table_slowdown_factor0_fpdiv_by32_f()) |
72 therm_grad_stepping_table_slowdown_factor3_f(
73 therm_grad_stepping_table_slowdown_factor0_fpdiv_by32_f()) |
74 therm_grad_stepping_table_slowdown_factor4_f(
75 therm_grad_stepping_table_slowdown_factor0_fpdiv_by32_f()));
76
77 v = gk20a_readl(g, therm_clk_timing_r(0));
78 v |= therm_clk_timing_grad_slowdown_enabled_f();
79 gk20a_writel(g, therm_clk_timing_r(0), v);
80
81 v = gk20a_readl(g, therm_config2_r());
82 v |= therm_config2_grad_enable_f(1);
83 v |= therm_config2_slowdown_factor_extended_f(1);
84 v = set_field(v, therm_config2_grad_step_duration_m(),
85 therm_config2_grad_step_duration_f(0));
86 gk20a_writel(g, therm_config2_r(), v);
87
88 gk20a_writel(g, therm_grad_stepping1_r(),
89 therm_grad_stepping1_pdiv_duration_f(0xbf4));
90
91 v = gk20a_readl(g, therm_grad_stepping0_r());
92 v |= therm_grad_stepping0_feature_enable_f();
93 gk20a_writel(g, therm_grad_stepping0_r(), v);
94
95 /* disable idle clock slowdown */
96 v = therm_clk_slowdown_2_idle_condition_a_select_f(0) |
97 therm_clk_slowdown_2_idle_condition_a_type_never_f() |
98 therm_clk_slowdown_2_idle_condition_b_type_never_f();
99 gk20a_writel(g, therm_clk_slowdown_2_r(0), v);
100
101 return 0;
102}
103
104int gv11b_elcg_init_idle_filters(struct gk20a *g)
105{
106 u32 gate_ctrl, idle_filter;
107 u32 engine_id;
108 u32 active_engine_id = 0;
109 struct fifo_gk20a *f = &g->fifo;
110
111 if (nvgpu_platform_is_simulation(g))
112 return 0;
113
114 nvgpu_log_info(g, "init clock/power gate reg");
115
116 for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
117 active_engine_id = f->active_engines_list[engine_id];
118
119 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
120 gate_ctrl = set_field(gate_ctrl,
121 therm_gate_ctrl_eng_idle_filt_exp_m(),
122 therm_gate_ctrl_eng_idle_filt_exp__prod_f());
123 gate_ctrl = set_field(gate_ctrl,
124 therm_gate_ctrl_eng_idle_filt_mant_m(),
125 therm_gate_ctrl_eng_idle_filt_mant__prod_f());
126 gate_ctrl = set_field(gate_ctrl,
127 therm_gate_ctrl_eng_delay_before_m(),
128 therm_gate_ctrl_eng_delay_before__prod_f());
129 gate_ctrl = set_field(gate_ctrl,
130 therm_gate_ctrl_eng_delay_after_m(),
131 therm_gate_ctrl_eng_delay_after__prod_f());
132 gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
133 }
134
135 idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
136 idle_filter = set_field(idle_filter,
137 therm_fecs_idle_filter_value_m(),
138 therm_fecs_idle_filter_value__prod_f());
139 gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
140
141 idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
142 idle_filter = set_field(idle_filter,
143 therm_hubmmu_idle_filter_value_m(),
144 therm_hubmmu_idle_filter_value__prod_f());
145 gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
146
147 return 0;
148}
diff --git a/drivers/gpu/nvgpu/gv11b/therm_gv11b.h b/drivers/gpu/nvgpu/gv11b/therm_gv11b.h
deleted file mode 100644
index bfe6231e..00000000
--- a/drivers/gpu/nvgpu/gv11b/therm_gv11b.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef THERM_GV11B_H
23#define THERM_GV11B_H
24
25struct gk20a;
26int gv11b_elcg_init_idle_filters(struct gk20a *g);
27int gv11b_init_therm_setup_hw(struct gk20a *g);
28
29#endif /* THERM_GV11B_H */