3 files changed, 0 insertions, 94 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 78cb1b98..3dedc6b5 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -3228,96 +3228,6 @@ void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
         }
 }
 
-static void gv11b_gr_write_sm_error_state(struct gk20a *g,
-                        u32 offset,
-                        struct nvgpu_tsg_sm_error_state *sm_error_states)
-{
-        nvgpu_writel(g,
-                gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset,
-                sm_error_states->hww_global_esr);
-        nvgpu_writel(g,
-                gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset,
-                sm_error_states->hww_warp_esr);
-        nvgpu_writel(g,
-                gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() + offset,
-                u64_lo32(sm_error_states->hww_warp_esr_pc));
-        nvgpu_writel(g,
-                gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r() + offset,
-                u64_hi32(sm_error_states->hww_warp_esr_pc));
-        nvgpu_writel(g,
-                gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset,
-                sm_error_states->hww_global_esr_report_mask);
-        nvgpu_writel(g,
-                gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset,
-                sm_error_states->hww_warp_esr_report_mask);
-}
-
-int gv11b_gr_update_sm_error_state(struct gk20a *g,
-                struct channel_gk20a *ch, u32 sm_id,
-                struct nvgpu_tsg_sm_error_state *sm_error_state)
-{
-        struct tsg_gk20a *tsg;
-        u32 gpc, tpc, sm, offset;
-        struct nvgpu_gr_ctx *ch_ctx;
-        int err = 0;
-        struct nvgpu_tsg_sm_error_state *tsg_sm_error_states;
-
-        tsg = tsg_gk20a_from_ch(ch);
-        if (tsg == NULL) {
-                return -EINVAL;
-        }
-
-        ch_ctx = &tsg->gr_ctx;
-
-        nvgpu_mutex_acquire(&g->dbg_sessions_lock);
-
-        tsg_sm_error_states = tsg->sm_error_states + sm_id;
-        gk20a_tsg_update_sm_error_state_locked(tsg, sm_id, sm_error_state);
-
-        err = gr_gk20a_disable_ctxsw(g);
-        if (err) {
-                nvgpu_err(g, "unable to stop gr ctxsw");
-                goto fail;
-        }
-
-        gpc = g->gr.sm_to_cluster[sm_id].gpc_index;
-        tpc = g->gr.sm_to_cluster[sm_id].tpc_index;
-        sm = g->gr.sm_to_cluster[sm_id].sm_index;
-
-        offset = gk20a_gr_gpc_offset(g, gpc) +
-                         gk20a_gr_tpc_offset(g, tpc) +
-                         gv11b_gr_sm_offset(g, sm);
-
-        if (gk20a_is_channel_ctx_resident(ch)) {
-                gv11b_gr_write_sm_error_state(g, offset, tsg_sm_error_states);
-        } else {
-                err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false);
-                if (err) {
-                        goto enable_ctxsw;
-                }
-
-                gr_gk20a_ctx_patch_write(g, ch_ctx,
-                        gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() +
-                        offset,
-                        tsg_sm_error_states->hww_global_esr_report_mask,
-                        true);
-                gr_gk20a_ctx_patch_write(g, ch_ctx,
-                        gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() +
-                        offset,
-                        tsg_sm_error_states->hww_warp_esr_report_mask,
-                        true);
-
-                gr_gk20a_ctx_patch_write_end(g, ch_ctx, false);
-        }
-
-enable_ctxsw:
-        err = gr_gk20a_enable_ctxsw(g);
-
-fail:
-        nvgpu_mutex_release(&g->dbg_sessions_lock);
-        return err;
-}
-
 int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
         struct channel_gk20a *ch, u64 sms, bool enable)
 {
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index a4b8fa91..20377acf 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -166,9 +166,6 @@ void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
                                 u32 *esr_sm_sel);
 int gv11b_gr_sm_trigger_suspend(struct gk20a *g);
 void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state);
-int gv11b_gr_update_sm_error_state(struct gk20a *g,
-                struct channel_gk20a *ch, u32 sm_id,
-                struct nvgpu_tsg_sm_error_state *sm_error_state);
 int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
         struct channel_gk20a *ch, u64 sms, bool enable);
 int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 479b06d1..591a7786 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -329,7 +329,6 @@ static const struct gpu_ops gv11b_ops = {
                 .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
                 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
                 .record_sm_error_state = gv11b_gr_record_sm_error_state,
-                .update_sm_error_state = gv11b_gr_update_sm_error_state,
                 .clear_sm_error_state = gm20b_gr_clear_sm_error_state,
                 .suspend_contexts = gr_gp10b_suspend_contexts,
                 .resume_contexts = gr_gk20a_resume_contexts,