summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gv11b
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c28
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.h5
2 files changed, 33 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 542ed1ff..7993e071 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -1069,6 +1069,31 @@ static void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data)
1069 gk20a_dbg_fn("done"); 1069 gk20a_dbg_fn("done");
1070} 1070}
1071 1071
1072static void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data)
1073{
1074 u32 val;
1075 bool flag;
1076
1077 gk20a_dbg_fn("");
1078
1079 val = gk20a_readl(g, gr_gpcs_tpcs_tex_in_dbg_r());
1080 flag = (data & NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE) ? 1 : 0;
1081 val = set_field(val, gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(),
1082 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(flag));
1083 gk20a_writel(g, gr_gpcs_tpcs_tex_in_dbg_r(), val);
1084
1085 val = gk20a_readl(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r());
1086 flag = (data &
1087 NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD) ? 1 : 0;
1088 val = set_field(val, gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(),
1089 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(flag));
1090 flag = (data &
1091 NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST) ? 1 : 0;
1092 val = set_field(val, gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(),
1093 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(flag));
1094 gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val);
1095}
1096
1072 1097
1073static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) 1098static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data)
1074{ 1099{
@@ -1120,6 +1145,9 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
1120 case NVC097_SET_COALESCE_BUFFER_SIZE: 1145 case NVC097_SET_COALESCE_BUFFER_SIZE:
1121 gr_gv11b_set_coalesce_buffer_size(g, data); 1146 gr_gv11b_set_coalesce_buffer_size(g, data);
1122 break; 1147 break;
1148 case NVC397_SET_TEX_IN_DBG:
1149 gr_gv11b_set_tex_in_dbg(g, data);
1150 break;
1123 default: 1151 default:
1124 goto fail; 1152 goto fail;
1125 } 1153 }
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 9283a597..ff5782d9 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -39,6 +39,11 @@ enum {
39#define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 39#define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280
40#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc 40#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
41#define NVC397_SET_GO_IDLE_TIMEOUT 0x022c 41#define NVC397_SET_GO_IDLE_TIMEOUT 0x022c
42#define NVC397_SET_TEX_IN_DBG 0x10bc
43
44#define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1
45#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2
46#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST 0x4
42 47
43#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 48#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0
44 49