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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/subctx_gv11b.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
index 607fff91..4f98d82a 100644
--- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Volta GPU series Subcontext 2 * Volta GPU series Subcontext
3 * 3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -103,9 +103,9 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c,
103 gv11b_subctx_commit_pdb(c, inst_block); 103 gv11b_subctx_commit_pdb(c, inst_block);
104 gv11b_subctx_commit_valid_mask(c, inst_block); 104 gv11b_subctx_commit_valid_mask(c, inst_block);
105 105
106 nvgpu_log(g, gpu_dbg_info, " subctx %d instblk set", c->t19x.subctx_id); 106 nvgpu_log(g, gpu_dbg_info, " subctx %d instblk set", c->subctx_id);
107 nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), 107 nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(),
108 ram_in_engine_wfi_veid_f(c->t19x.subctx_id)); 108 ram_in_engine_wfi_veid_f(c->subctx_id));
109 109
110} 110}
111 111
@@ -206,7 +206,7 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c,
206 ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); 206 ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo);
207 nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", 207 nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x",
208 format_word, pdb_addr_hi); 208 format_word, pdb_addr_hi);
209 for (subctx_id = 0; subctx_id < f->t19x.max_subctx_count; subctx_id++) { 209 for (subctx_id = 0; subctx_id < f->max_subctx_count; subctx_id++) {
210 lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); 210 lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id);
211 hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); 211 hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id);
212 nvgpu_mem_wr32(g, inst_block, lo, format_word); 212 nvgpu_mem_wr32(g, inst_block, lo, format_word);