diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 27 |
1 files changed, 18 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 80d6be3d..60ffdb98 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | |||
@@ -340,10 +340,12 @@ void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0) | |||
340 | pwr_pmu_falcon_ecc_status_reset_task_f()); | 340 | pwr_pmu_falcon_ecc_status_reset_task_f()); |
341 | 341 | ||
342 | /* update counters per slice */ | 342 | /* update counters per slice */ |
343 | if (corrected_overflow) | 343 | if (corrected_overflow) { |
344 | corrected_delta += (0x1UL << pwr_pmu_falcon_ecc_corrected_err_count_total_s()); | 344 | corrected_delta += (0x1UL << pwr_pmu_falcon_ecc_corrected_err_count_total_s()); |
345 | if (uncorrected_overflow) | 345 | } |
346 | if (uncorrected_overflow) { | ||
346 | uncorrected_delta += (0x1UL << pwr_pmu_falcon_ecc_uncorrected_err_count_total_s()); | 347 | uncorrected_delta += (0x1UL << pwr_pmu_falcon_ecc_uncorrected_err_count_total_s()); |
348 | } | ||
347 | 349 | ||
348 | g->ecc.pmu.pmu_ecc_corrected_err_count[0].counter += corrected_delta; | 350 | g->ecc.pmu.pmu_ecc_corrected_err_count[0].counter += corrected_delta; |
349 | g->ecc.pmu.pmu_ecc_uncorrected_err_count[0].counter += uncorrected_delta; | 351 | g->ecc.pmu.pmu_ecc_uncorrected_err_count[0].counter += uncorrected_delta; |
@@ -351,21 +353,26 @@ void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0) | |||
351 | nvgpu_log(g, gpu_dbg_intr, | 353 | nvgpu_log(g, gpu_dbg_intr, |
352 | "pmu ecc interrupt intr1: 0x%x", intr1); | 354 | "pmu ecc interrupt intr1: 0x%x", intr1); |
353 | 355 | ||
354 | if (ecc_status & pwr_pmu_falcon_ecc_status_corrected_err_imem_m()) | 356 | if (ecc_status & pwr_pmu_falcon_ecc_status_corrected_err_imem_m()) { |
355 | nvgpu_log(g, gpu_dbg_intr, | 357 | nvgpu_log(g, gpu_dbg_intr, |
356 | "imem ecc error corrected"); | 358 | "imem ecc error corrected"); |
357 | if (ecc_status & pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m()) | 359 | } |
360 | if (ecc_status & pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m()) { | ||
358 | nvgpu_log(g, gpu_dbg_intr, | 361 | nvgpu_log(g, gpu_dbg_intr, |
359 | "imem ecc error uncorrected"); | 362 | "imem ecc error uncorrected"); |
360 | if (ecc_status & pwr_pmu_falcon_ecc_status_corrected_err_dmem_m()) | 363 | } |
364 | if (ecc_status & pwr_pmu_falcon_ecc_status_corrected_err_dmem_m()) { | ||
361 | nvgpu_log(g, gpu_dbg_intr, | 365 | nvgpu_log(g, gpu_dbg_intr, |
362 | "dmem ecc error corrected"); | 366 | "dmem ecc error corrected"); |
363 | if (ecc_status & pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_m()) | 367 | } |
368 | if (ecc_status & pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_m()) { | ||
364 | nvgpu_log(g, gpu_dbg_intr, | 369 | nvgpu_log(g, gpu_dbg_intr, |
365 | "dmem ecc error uncorrected"); | 370 | "dmem ecc error uncorrected"); |
371 | } | ||
366 | 372 | ||
367 | if (corrected_overflow || uncorrected_overflow) | 373 | if (corrected_overflow || uncorrected_overflow) { |
368 | nvgpu_info(g, "ecc counter overflow!"); | 374 | nvgpu_info(g, "ecc counter overflow!"); |
375 | } | ||
369 | 376 | ||
370 | nvgpu_log(g, gpu_dbg_intr, | 377 | nvgpu_log(g, gpu_dbg_intr, |
371 | "ecc error row address: 0x%x", | 378 | "ecc error row address: 0x%x", |
@@ -456,8 +463,9 @@ int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) | |||
456 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 463 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
457 | pmu_handle_pg_param_msg, pmu, &seq, ~0); | 464 | pmu_handle_pg_param_msg, pmu, &seq, ~0); |
458 | 465 | ||
459 | } else | 466 | } else { |
460 | return -EINVAL; | 467 | return -EINVAL; |
468 | } | ||
461 | 469 | ||
462 | return 0; | 470 | return 0; |
463 | } | 471 | } |
@@ -493,8 +501,9 @@ int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) | |||
493 | gv11b_dbg_pmu(g, "cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n"); | 501 | gv11b_dbg_pmu(g, "cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n"); |
494 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 502 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
495 | pmu_handle_pg_sub_feature_msg, pmu, &seq, ~0); | 503 | pmu_handle_pg_sub_feature_msg, pmu, &seq, ~0); |
496 | } else | 504 | } else { |
497 | return -EINVAL; | 505 | return -EINVAL; |
506 | } | ||
498 | 507 | ||
499 | return 0; | 508 | return 0; |
500 | } | 509 | } |