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path: root/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/mc_gv11b.c19
1 files changed, 11 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
index 8b8fcea0..cc29f74a 100644
--- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
@@ -30,6 +30,10 @@ static void mc_gv11b_intr_enable(struct gk20a *g)
30 30
31 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 31 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
32 0xffffffff); 32 0xffffffff);
33 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
34 0xffffffff);
35 gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL);
36
33 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = 37 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
34 mc_intr_pfifo_pending_f() | 38 mc_intr_pfifo_pending_f() |
35 mc_intr_hub_pending_f() | 39 mc_intr_hub_pending_f() |
@@ -38,20 +42,19 @@ static void mc_gv11b_intr_enable(struct gk20a *g)
38 mc_intr_ltc_pending_f() | 42 mc_intr_ltc_pending_f() |
39 eng_intr_mask; 43 eng_intr_mask;
40 44
41 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
42 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
43
44 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
45 0xffffffff);
46 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = 45 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
47 mc_intr_pfifo_pending_f() 46 mc_intr_pfifo_pending_f()
48 | eng_intr_mask; 47 | eng_intr_mask;
48
49 /* TODO: Enable PRI faults for HUB ECC err intr */
50 gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types);
51
52 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
53 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
54
49 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), 55 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
50 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); 56 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
51 57
52 /* TODO: Enable PRI faults for HUB ECC err intr */
53 gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX,
54 HUB_INTR_TYPE_ECC_UNCORRECTED);
55} 58}
56 59
57static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) 60static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)