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path: root/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/ltc_gv11b.c10
1 files changed, 2 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
index 48faa4d2..db797bde 100644
--- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
@@ -90,13 +90,11 @@ void gv11b_ltc_isr(struct gk20a *g)
90 u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; 90 u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt;
91 u32 corrected_delta, uncorrected_delta; 91 u32 corrected_delta, uncorrected_delta;
92 u32 corrected_overflow, uncorrected_overflow; 92 u32 corrected_overflow, uncorrected_overflow;
93 u32 ltc_corrected, ltc_uncorrected;
94 93
95 mc_intr = gk20a_readl(g, mc_intr_ltc_r()); 94 mc_intr = gk20a_readl(g, mc_intr_ltc_r());
96 for (ltc = 0; ltc < g->ltc_count; ltc++) { 95 for (ltc = 0; ltc < g->ltc_count; ltc++) {
97 if ((mc_intr & 1U << ltc) == 0) 96 if ((mc_intr & 1U << ltc) == 0)
98 continue; 97 continue;
99 ltc_corrected = ltc_uncorrected = 0U;
100 98
101 for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { 99 for (slice = 0; slice < g->gr.slices_per_ltc; slice++) {
102 u32 offset = ltc_stride * ltc + lts_stride * slice; 100 u32 offset = ltc_stride * ltc + lts_stride * slice;
@@ -150,8 +148,8 @@ void gv11b_ltc_isr(struct gk20a *g)
150 if (uncorrected_overflow) 148 if (uncorrected_overflow)
151 uncorrected_delta += (0x1U << ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s()); 149 uncorrected_delta += (0x1U << ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s());
152 150
153 ltc_corrected += corrected_delta; 151 g->ecc.ltc.ecc_sec_count[ltc][slice].counter += corrected_delta;
154 ltc_uncorrected += uncorrected_delta; 152 g->ecc.ltc.ecc_ded_count[ltc][slice].counter += uncorrected_delta;
155 nvgpu_log(g, gpu_dbg_intr, 153 nvgpu_log(g, gpu_dbg_intr,
156 "ltc:%d lts: %d cache ecc interrupt intr: 0x%x", ltc, slice, ltc_intr3); 154 "ltc:%d lts: %d cache ecc interrupt intr: 0x%x", ltc, slice, ltc_intr3);
157 155
@@ -177,10 +175,6 @@ void gv11b_ltc_isr(struct gk20a *g)
177 } 175 }
178 176
179 } 177 }
180 g->ecc.ltc.l2_cache_corrected_err_count.counters[ltc] +=
181 ltc_corrected;
182 g->ecc.ltc.l2_cache_uncorrected_err_count.counters[ltc] +=
183 ltc_uncorrected;
184 178
185 } 179 }
186 180