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path: root/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c36
1 files changed, 24 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 0c5776f0..c6c8e18c 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -55,6 +55,7 @@
55#include "gp10b/gr_gp10b.h" 55#include "gp10b/gr_gp10b.h"
56 56
57#include "gp106/pmu_gp106.h" 57#include "gp106/pmu_gp106.h"
58#include "gp106/acr_gp106.h"
58 59
59#include "hal_gv11b.h" 60#include "hal_gv11b.h"
60#include "gr_gv11b.h" 61#include "gr_gv11b.h"
@@ -65,6 +66,7 @@
65#include "gr_ctx_gv11b.h" 66#include "gr_ctx_gv11b.h"
66#include "mm_gv11b.h" 67#include "mm_gv11b.h"
67#include "pmu_gv11b.h" 68#include "pmu_gv11b.h"
69#include "acr_gv11b.h"
68#include "fb_gv11b.h" 70#include "fb_gv11b.h"
69#include "fifo_gv11b.h" 71#include "fifo_gv11b.h"
70#include "gv11b_gating_reglist.h" 72#include "gv11b_gating_reglist.h"
@@ -79,6 +81,7 @@
79#include <nvgpu/hw/gv11b/hw_ram_gv11b.h> 81#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
80#include <nvgpu/hw/gv11b/hw_top_gv11b.h> 82#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
81#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h> 83#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
84#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
82 85
83static int gv11b_get_litter_value(struct gk20a *g, int value) 86static int gv11b_get_litter_value(struct gk20a *g, int value)
84{ 87{
@@ -633,6 +636,8 @@ int gv11b_init_hal(struct gk20a *g)
633{ 636{
634 struct gpu_ops *gops = &g->ops; 637 struct gpu_ops *gops = &g->ops;
635 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; 638 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
639 u32 val;
640 bool priv_security;
636 641
637 gops->ltc = gv11b_ops.ltc; 642 gops->ltc = gv11b_ops.ltc;
638 gops->ce2 = gv11b_ops.ce2; 643 gops->ce2 = gv11b_ops.ce2;
@@ -661,33 +666,38 @@ int gv11b_init_hal(struct gk20a *g)
661 gv11b_ops.chip_init_gpu_characteristics; 666 gv11b_ops.chip_init_gpu_characteristics;
662 gops->get_litter_value = gv11b_ops.get_litter_value; 667 gops->get_litter_value = gv11b_ops.get_litter_value;
663 668
664 /* boot in non-secure modes for time being */ 669 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
670 if (val) {
671 priv_security = true;
672 pr_err("priv security is enabled\n");
673 } else {
674 priv_security = false;
675 pr_err("priv security is disabled\n");
676 }
665 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); 677 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);
666 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); 678 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security);
667 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); 679 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security);
668 680
669 /* priv security dependent ops */ 681 /* priv security dependent ops */
670 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { 682 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
671 /* Add in ops from gm20b acr */ 683 /* Add in ops from gm20b acr */
672 gops->pmu.prepare_ucode = prepare_ucode_blob, 684 gops->pmu.prepare_ucode = gp106_prepare_ucode_blob,
673 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn, 685 gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn,
674 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap,
675 gops->pmu.is_priv_load = gm20b_is_priv_load,
676 gops->pmu.get_wpr = gm20b_wpr_info, 686 gops->pmu.get_wpr = gm20b_wpr_info,
677 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, 687 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
678 gops->pmu.pmu_populate_loader_cfg = 688 gops->pmu.pmu_populate_loader_cfg =
679 gm20b_pmu_populate_loader_cfg, 689 gp106_pmu_populate_loader_cfg,
680 gops->pmu.flcn_populate_bl_dmem_desc = 690 gops->pmu.flcn_populate_bl_dmem_desc =
681 gm20b_flcn_populate_bl_dmem_desc, 691 gp106_flcn_populate_bl_dmem_desc,
682 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, 692 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
683 gops->pmu.falcon_clear_halt_interrupt_status = 693 gops->pmu.falcon_clear_halt_interrupt_status =
684 clear_halt_interrupt_status, 694 clear_halt_interrupt_status,
685 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, 695 gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1,
686 696
687 gops->pmu.init_wpr_region = gm20b_pmu_init_acr; 697 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
688 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; 698 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
689 gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; 699 gops->pmu.is_lazy_bootstrap = gv11b_is_lazy_bootstrap,
690 gops->pmu.is_priv_load = gp10b_is_priv_load; 700 gops->pmu.is_priv_load = gv11b_is_priv_load,
691 701
692 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; 702 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
693 } else { 703 } else {
@@ -702,8 +712,10 @@ int gv11b_init_hal(struct gk20a *g)
702 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; 712 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
703 } 713 }
704 714
715 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
705 gv11b_init_uncompressed_kind_map(); 716 gv11b_init_uncompressed_kind_map();
706 gv11b_init_kind_attr(); 717 gv11b_init_kind_attr();
718 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
707 719
708 g->name = "gv11b"; 720 g->name = "gv11b";
709 721