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path: root/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c778
1 files changed, 778 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
new file mode 100644
index 00000000..fc059caa
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -0,0 +1,778 @@
1/*
2 * GV11B Tegra HAL interface
3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <linux/types.h>
26#include <linux/printk.h>
27
28#include <linux/types.h>
29#include <linux/tegra_gpu_t19x.h>
30
31#include "gk20a/gk20a.h"
32#include "gk20a/fifo_gk20a.h"
33#include "gk20a/fecs_trace_gk20a.h"
34#include "gk20a/css_gr_gk20a.h"
35#include "gk20a/mc_gk20a.h"
36#include "gk20a/mm_gk20a.h"
37#include "gk20a/dbg_gpu_gk20a.h"
38#include "gk20a/bus_gk20a.h"
39#include "gk20a/flcn_gk20a.h"
40#include "gk20a/regops_gk20a.h"
41#include "gk20a/fb_gk20a.h"
42#include "gk20a/pmu_gk20a.h"
43#include "gk20a/gr_gk20a.h"
44
45#include "gm20b/ltc_gm20b.h"
46#include "gm20b/gr_gm20b.h"
47#include "gm20b/fb_gm20b.h"
48#include "gm20b/fifo_gm20b.h"
49#include "gm20b/mm_gm20b.h"
50#include "gm20b/acr_gm20b.h"
51#include "gm20b/pmu_gm20b.h"
52
53#include "gp10b/ltc_gp10b.h"
54#include "gp10b/therm_gp10b.h"
55#include "gp10b/mc_gp10b.h"
56#include "gp10b/ce_gp10b.h"
57#include "gp10b/priv_ring_gp10b.h"
58#include "gp10b/fifo_gp10b.h"
59#include "gp10b/fecs_trace_gp10b.h"
60#include "gp10b/fb_gp10b.h"
61#include "gp10b/mm_gp10b.h"
62#include "gp10b/pmu_gp10b.h"
63#include "gp10b/gr_gp10b.h"
64
65#include "gp106/pmu_gp106.h"
66#include "gp106/acr_gp106.h"
67
68#include "gv100/gr_gv100.h"
69
70#include "dbg_gpu_gv11b.h"
71#include "hal_gv11b.h"
72#include "css_gr_gv11b.h"
73#include "gr_gv11b.h"
74#include "mc_gv11b.h"
75#include "ltc_gv11b.h"
76#include "gv11b.h"
77#include "ce_gv11b.h"
78#include "gr_ctx_gv11b.h"
79#include "mm_gv11b.h"
80#include "pmu_gv11b.h"
81#include "acr_gv11b.h"
82#include "fb_gv11b.h"
83#include "fifo_gv11b.h"
84#include "gv11b_gating_reglist.h"
85#include "regops_gv11b.h"
86#include "subctx_gv11b.h"
87#include "therm_gv11b.h"
88
89#include <nvgpu/bus.h>
90#include <nvgpu/debug.h>
91#include <nvgpu/enabled.h>
92#include <nvgpu/ctxsw_trace.h>
93
94#include <nvgpu/hw/gv11b/hw_proj_gv11b.h>
95#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
96#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
97#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
98#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
99#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
100
101int gv11b_get_litter_value(struct gk20a *g, int value)
102{
103 int ret = EINVAL;
104 switch (value) {
105 case GPU_LIT_NUM_GPCS:
106 ret = proj_scal_litter_num_gpcs_v();
107 break;
108 case GPU_LIT_NUM_PES_PER_GPC:
109 ret = proj_scal_litter_num_pes_per_gpc_v();
110 break;
111 case GPU_LIT_NUM_ZCULL_BANKS:
112 ret = proj_scal_litter_num_zcull_banks_v();
113 break;
114 case GPU_LIT_NUM_TPC_PER_GPC:
115 ret = proj_scal_litter_num_tpc_per_gpc_v();
116 break;
117 case GPU_LIT_NUM_SM_PER_TPC:
118 ret = proj_scal_litter_num_sm_per_tpc_v();
119 break;
120 case GPU_LIT_NUM_FBPS:
121 ret = proj_scal_litter_num_fbps_v();
122 break;
123 case GPU_LIT_GPC_BASE:
124 ret = proj_gpc_base_v();
125 break;
126 case GPU_LIT_GPC_STRIDE:
127 ret = proj_gpc_stride_v();
128 break;
129 case GPU_LIT_GPC_SHARED_BASE:
130 ret = proj_gpc_shared_base_v();
131 break;
132 case GPU_LIT_TPC_IN_GPC_BASE:
133 ret = proj_tpc_in_gpc_base_v();
134 break;
135 case GPU_LIT_TPC_IN_GPC_STRIDE:
136 ret = proj_tpc_in_gpc_stride_v();
137 break;
138 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
139 ret = proj_tpc_in_gpc_shared_base_v();
140 break;
141 case GPU_LIT_PPC_IN_GPC_BASE:
142 ret = proj_ppc_in_gpc_base_v();
143 break;
144 case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
145 ret = proj_ppc_in_gpc_shared_base_v();
146 break;
147 case GPU_LIT_PPC_IN_GPC_STRIDE:
148 ret = proj_ppc_in_gpc_stride_v();
149 break;
150 case GPU_LIT_ROP_BASE:
151 ret = proj_rop_base_v();
152 break;
153 case GPU_LIT_ROP_STRIDE:
154 ret = proj_rop_stride_v();
155 break;
156 case GPU_LIT_ROP_SHARED_BASE:
157 ret = proj_rop_shared_base_v();
158 break;
159 case GPU_LIT_HOST_NUM_ENGINES:
160 ret = proj_host_num_engines_v();
161 break;
162 case GPU_LIT_HOST_NUM_PBDMA:
163 ret = proj_host_num_pbdma_v();
164 break;
165 case GPU_LIT_LTC_STRIDE:
166 ret = proj_ltc_stride_v();
167 break;
168 case GPU_LIT_LTS_STRIDE:
169 ret = proj_lts_stride_v();
170 break;
171 case GPU_LIT_SM_PRI_STRIDE:
172 ret = proj_sm_stride_v();
173 break;
174 case GPU_LIT_SMPC_PRI_BASE:
175 ret = proj_smpc_base_v();
176 break;
177 case GPU_LIT_SMPC_PRI_SHARED_BASE:
178 ret = proj_smpc_shared_base_v();
179 break;
180 case GPU_LIT_SMPC_PRI_UNIQUE_BASE:
181 ret = proj_smpc_unique_base_v();
182 break;
183 case GPU_LIT_SMPC_PRI_STRIDE:
184 ret = proj_smpc_stride_v();
185 break;
186 /* Even though GV11B doesn't have an FBPA unit, the HW reports one,
187 * and the microcode as a result leaves space in the context buffer
188 * for one, so make sure SW accounts for this also.
189 */
190 case GPU_LIT_NUM_FBPAS:
191 ret = proj_scal_litter_num_fbpas_v();
192 break;
193 /* Hardcode FBPA values other than NUM_FBPAS to 0. */
194 case GPU_LIT_FBPA_STRIDE:
195 case GPU_LIT_FBPA_BASE:
196 case GPU_LIT_FBPA_SHARED_BASE:
197 ret = 0;
198 break;
199 case GPU_LIT_TWOD_CLASS:
200 ret = FERMI_TWOD_A;
201 break;
202 case GPU_LIT_THREED_CLASS:
203 ret = VOLTA_A;
204 break;
205 case GPU_LIT_COMPUTE_CLASS:
206 ret = VOLTA_COMPUTE_A;
207 break;
208 case GPU_LIT_GPFIFO_CLASS:
209 ret = VOLTA_CHANNEL_GPFIFO_A;
210 break;
211 case GPU_LIT_I2M_CLASS:
212 ret = KEPLER_INLINE_TO_MEMORY_B;
213 break;
214 case GPU_LIT_DMA_COPY_CLASS:
215 ret = VOLTA_DMA_COPY_A;
216 break;
217
218 default:
219 nvgpu_err(g, "Missing definition %d", value);
220 BUG();
221 break;
222 }
223
224 return ret;
225}
226
227static const struct gpu_ops gv11b_ops = {
228 .ltc = {
229 .determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
230 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
231 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
232 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
233 .init_cbc = NULL,
234 .init_fs_state = gv11b_ltc_init_fs_state,
235 .init_comptags = gp10b_ltc_init_comptags,
236 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
237 .isr = gv11b_ltc_isr,
238 .cbc_fix_config = gv11b_ltc_cbc_fix_config,
239 .flush = gm20b_flush_ltc,
240 .set_enabled = gp10b_ltc_set_enabled,
241 },
242 .ce2 = {
243 .isr_stall = gv11b_ce_isr,
244 .isr_nonstall = gp10b_ce_nonstall_isr,
245 .get_num_pce = gv11b_ce_get_num_pce,
246 },
247 .gr = {
248 .get_patch_slots = gr_gv100_get_patch_slots,
249 .init_gpc_mmu = gr_gv11b_init_gpc_mmu,
250 .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults,
251 .cb_size_default = gr_gv11b_cb_size_default,
252 .calc_global_ctx_buffer_size =
253 gr_gv11b_calc_global_ctx_buffer_size,
254 .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb,
255 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
256 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
257 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
258 .handle_sw_method = gr_gv11b_handle_sw_method,
259 .set_alpha_circular_buffer_size =
260 gr_gv11b_set_alpha_circular_buffer_size,
261 .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
262 .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions,
263 .is_valid_class = gr_gv11b_is_valid_class,
264 .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class,
265 .is_valid_compute_class = gr_gv11b_is_valid_compute_class,
266 .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
267 .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
268 .init_fs_state = gr_gv11b_init_fs_state,
269 .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
270 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
271 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
272 .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask,
273 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
274 .free_channel_ctx = gk20a_free_channel_ctx,
275 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
276 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull,
277 .get_zcull_info = gr_gk20a_get_zcull_info,
278 .is_tpc_addr = gr_gm20b_is_tpc_addr,
279 .get_tpc_num = gr_gm20b_get_tpc_num,
280 .detect_sm_arch = gr_gv11b_detect_sm_arch,
281 .add_zbc_color = gr_gp10b_add_zbc_color,
282 .add_zbc_depth = gr_gp10b_add_zbc_depth,
283 .zbc_set_table = gk20a_gr_zbc_set_table,
284 .zbc_query_table = gr_gk20a_query_zbc,
285 .pmu_save_zbc = gk20a_pmu_save_zbc,
286 .add_zbc = gr_gk20a_add_zbc,
287 .pagepool_default_size = gr_gv11b_pagepool_default_size,
288 .init_ctx_state = gr_gp10b_init_ctx_state,
289 .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx,
290 .free_gr_ctx = gr_gp10b_free_gr_ctx,
291 .update_ctxsw_preemption_mode =
292 gr_gp10b_update_ctxsw_preemption_mode,
293 .dump_gr_regs = gr_gv11b_dump_gr_status_regs,
294 .update_pc_sampling = gr_gm20b_update_pc_sampling,
295 .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
296 .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp,
297 .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc,
298 .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
299 .get_max_fbps_count = gr_gm20b_get_max_fbps_count,
300 .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
301 .wait_empty = gr_gv11b_wait_empty,
302 .init_cyclestats = gr_gm20b_init_cyclestats,
303 .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode,
304 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
305 .bpt_reg_info = gv11b_gr_bpt_reg_info,
306 .get_access_map = gr_gv11b_get_access_map,
307 .handle_fecs_error = gr_gv11b_handle_fecs_error,
308 .handle_sm_exception = gr_gk20a_handle_sm_exception,
309 .handle_tex_exception = gr_gv11b_handle_tex_exception,
310 .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions,
311 .enable_exceptions = gr_gv11b_enable_exceptions,
312 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
313 .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
314 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
315 .record_sm_error_state = gv11b_gr_record_sm_error_state,
316 .update_sm_error_state = gv11b_gr_update_sm_error_state,
317 .clear_sm_error_state = gm20b_gr_clear_sm_error_state,
318 .suspend_contexts = gr_gp10b_suspend_contexts,
319 .resume_contexts = gr_gk20a_resume_contexts,
320 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
321 .init_sm_id_table = gr_gv100_init_sm_id_table,
322 .load_smid_config = gr_gv11b_load_smid_config,
323 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
324 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
325 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
326 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
327 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
328 .setup_rop_mapping = gr_gv11b_setup_rop_mapping,
329 .program_zcull_mapping = gr_gv11b_program_zcull_mapping,
330 .commit_global_timeslice = gr_gv11b_commit_global_timeslice,
331 .commit_inst = gr_gv11b_commit_inst,
332 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
333 .write_pm_ptr = gr_gv11b_write_pm_ptr,
334 .init_elcg_mode = gr_gv11b_init_elcg_mode,
335 .load_tpc_mask = gr_gv11b_load_tpc_mask,
336 .inval_icache = gr_gk20a_inval_icache,
337 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
338 .wait_for_pause = gr_gk20a_wait_for_pause,
339 .resume_from_pause = gv11b_gr_resume_from_pause,
340 .clear_sm_errors = gr_gk20a_clear_sm_errors,
341 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
342 .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel,
343 .sm_debugger_attached = gv11b_gr_sm_debugger_attached,
344 .suspend_single_sm = gv11b_gr_suspend_single_sm,
345 .suspend_all_sms = gv11b_gr_suspend_all_sms,
346 .resume_single_sm = gv11b_gr_resume_single_sm,
347 .resume_all_sms = gv11b_gr_resume_all_sms,
348 .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr,
349 .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr,
350 .get_sm_no_lock_down_hww_global_esr_mask =
351 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask,
352 .lock_down_sm = gv11b_gr_lock_down_sm,
353 .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down,
354 .clear_sm_hww = gv11b_gr_clear_sm_hww,
355 .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf,
356 .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs,
357 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
358 .set_boosted_ctx = gr_gp10b_set_boosted_ctx,
359 .set_preemption_mode = gr_gp10b_set_preemption_mode,
360 .set_czf_bypass = NULL,
361 .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
362 .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
363 .init_preemption_state = NULL,
364 .update_boosted_ctx = gr_gp10b_update_boosted_ctx,
365 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
366 .create_gr_sysfs = gr_gv11b_create_sysfs,
367 .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode,
368 .is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
369 .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
370 .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
371 .zbc_s_query_table = gr_gv11b_zbc_s_query_table,
372 .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl,
373 .handle_gpc_gpcmmu_exception =
374 gr_gv11b_handle_gpc_gpcmmu_exception,
375 .add_zbc_type_s = gr_gv11b_add_zbc_type_s,
376 .get_egpc_base = gv11b_gr_get_egpc_base,
377 .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
378 .handle_gpc_gpccs_exception =
379 gr_gv11b_handle_gpc_gpccs_exception,
380 .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl,
381 .access_smpc_reg = gv11b_gr_access_smpc_reg,
382 .is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
383 .add_zbc_s = gr_gv11b_add_zbc_stencil,
384 .handle_gcc_exception = gr_gv11b_handle_gcc_exception,
385 .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle,
386 .handle_tpc_sm_ecc_exception =
387 gr_gv11b_handle_tpc_sm_ecc_exception,
388 .decode_egpc_addr = gv11b_gr_decode_egpc_addr,
389 .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data,
390 },
391 .fb = {
392 .reset = gv11b_fb_reset,
393 .init_hw = gk20a_fb_init_hw,
394 .init_fs_state = gv11b_fb_init_fs_state,
395 .init_cbc = gv11b_fb_init_cbc,
396 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
397 .set_use_full_comp_tag_line =
398 gm20b_fb_set_use_full_comp_tag_line,
399 .compression_page_size = gp10b_fb_compression_page_size,
400 .compressible_page_size = gp10b_fb_compressible_page_size,
401 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
402 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
403 .read_wpr_info = gm20b_fb_read_wpr_info,
404 .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
405 .set_debug_mode = gm20b_fb_set_debug_mode,
406 .tlb_invalidate = gk20a_fb_tlb_invalidate,
407 .hub_isr = gv11b_fb_hub_isr,
408 .mem_unlock = NULL,
409 },
410 .clock_gating = {
411 .slcg_bus_load_gating_prod =
412 gv11b_slcg_bus_load_gating_prod,
413 .slcg_ce2_load_gating_prod =
414 gv11b_slcg_ce2_load_gating_prod,
415 .slcg_chiplet_load_gating_prod =
416 gv11b_slcg_chiplet_load_gating_prod,
417 .slcg_ctxsw_firmware_load_gating_prod =
418 gv11b_slcg_ctxsw_firmware_load_gating_prod,
419 .slcg_fb_load_gating_prod =
420 gv11b_slcg_fb_load_gating_prod,
421 .slcg_fifo_load_gating_prod =
422 gv11b_slcg_fifo_load_gating_prod,
423 .slcg_gr_load_gating_prod =
424 gr_gv11b_slcg_gr_load_gating_prod,
425 .slcg_ltc_load_gating_prod =
426 ltc_gv11b_slcg_ltc_load_gating_prod,
427 .slcg_perf_load_gating_prod =
428 gv11b_slcg_perf_load_gating_prod,
429 .slcg_priring_load_gating_prod =
430 gv11b_slcg_priring_load_gating_prod,
431 .slcg_pmu_load_gating_prod =
432 gv11b_slcg_pmu_load_gating_prod,
433 .slcg_therm_load_gating_prod =
434 gv11b_slcg_therm_load_gating_prod,
435 .slcg_xbar_load_gating_prod =
436 gv11b_slcg_xbar_load_gating_prod,
437 .blcg_bus_load_gating_prod =
438 gv11b_blcg_bus_load_gating_prod,
439 .blcg_ce_load_gating_prod =
440 gv11b_blcg_ce_load_gating_prod,
441 .blcg_ctxsw_firmware_load_gating_prod =
442 gv11b_blcg_ctxsw_firmware_load_gating_prod,
443 .blcg_fb_load_gating_prod =
444 gv11b_blcg_fb_load_gating_prod,
445 .blcg_fifo_load_gating_prod =
446 gv11b_blcg_fifo_load_gating_prod,
447 .blcg_gr_load_gating_prod =
448 gv11b_blcg_gr_load_gating_prod,
449 .blcg_ltc_load_gating_prod =
450 gv11b_blcg_ltc_load_gating_prod,
451 .blcg_pwr_csb_load_gating_prod =
452 gv11b_blcg_pwr_csb_load_gating_prod,
453 .blcg_pmu_load_gating_prod =
454 gv11b_blcg_pmu_load_gating_prod,
455 .blcg_xbar_load_gating_prod =
456 gv11b_blcg_xbar_load_gating_prod,
457 .pg_gr_load_gating_prod =
458 gr_gv11b_pg_gr_load_gating_prod,
459 },
460 .fifo = {
461 .get_preempt_timeout = gv11b_fifo_get_preempt_timeout,
462 .init_fifo_setup_hw = gv11b_init_fifo_setup_hw,
463 .bind_channel = channel_gm20b_bind,
464 .unbind_channel = channel_gv11b_unbind,
465 .disable_channel = gk20a_fifo_disable_channel,
466 .enable_channel = gk20a_fifo_enable_channel,
467 .alloc_inst = gk20a_fifo_alloc_inst,
468 .free_inst = gk20a_fifo_free_inst,
469 .setup_ramfc = channel_gv11b_setup_ramfc,
470 .channel_set_timeslice = gk20a_fifo_set_timeslice,
471 .default_timeslice_us = gk20a_fifo_default_timeslice_us,
472 .setup_userd = gk20a_fifo_setup_userd,
473 .userd_gp_get = gv11b_userd_gp_get,
474 .userd_gp_put = gv11b_userd_gp_put,
475 .userd_pb_get = gv11b_userd_pb_get,
476 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
477 .preempt_channel = gv11b_fifo_preempt_channel,
478 .preempt_tsg = gv11b_fifo_preempt_tsg,
479 .enable_tsg = gv11b_fifo_enable_tsg,
480 .disable_tsg = gk20a_disable_tsg,
481 .tsg_verify_channel_status = gk20a_fifo_tsg_unbind_channel_verify_status,
482 .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload,
483 .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted,
484 .update_runlist = gk20a_fifo_update_runlist,
485 .trigger_mmu_fault = NULL,
486 .get_mmu_fault_info = NULL,
487 .wait_engine_idle = gk20a_fifo_wait_engine_idle,
488 .get_num_fifos = gv11b_fifo_get_num_fifos,
489 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
490 .set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
491 .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
492 .force_reset_ch = gk20a_fifo_force_reset_ch,
493 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
494 .device_info_data_parse = gp10b_device_info_data_parse,
495 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
496 .init_engine_info = gk20a_fifo_init_engine_info,
497 .runlist_entry_size = ram_rl_entry_size_v,
498 .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
499 .get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
500 .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
501 .dump_pbdma_status = gk20a_dump_pbdma_status,
502 .dump_eng_status = gv11b_dump_eng_status,
503 .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
504 .intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
505 .is_preempt_pending = gv11b_fifo_is_preempt_pending,
506 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs,
507 .reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
508 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
509 .handle_sched_error = gv11b_fifo_handle_sched_error,
510 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0,
511 .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1,
512 .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers,
513 .deinit_eng_method_buffers =
514 gv11b_fifo_deinit_eng_method_buffers,
515 .tsg_bind_channel = gk20a_tsg_bind_channel,
516 .tsg_unbind_channel = gk20a_tsg_unbind_channel,
517#ifdef CONFIG_TEGRA_GK20A_NVHOST
518 .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf,
519 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
520 .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd,
521 .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
522 .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
523 .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
524#endif
525 .resetup_ramfc = NULL,
526 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
527 .free_channel_ctx_header = gv11b_free_subctx_header,
528 .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
529 .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
530 },
531 .gr_ctx = {
532 .get_netlist_name = gr_gv11b_get_netlist_name,
533 .is_fw_defined = gr_gv11b_is_firmware_defined,
534 },
535#ifdef CONFIG_GK20A_CTXSW_TRACE
536 .fecs_trace = {
537 .alloc_user_buffer = NULL,
538 .free_user_buffer = NULL,
539 .mmap_user_buffer = NULL,
540 .init = NULL,
541 .deinit = NULL,
542 .enable = NULL,
543 .disable = NULL,
544 .is_enabled = NULL,
545 .reset = NULL,
546 .flush = NULL,
547 .poll = NULL,
548 .bind_channel = NULL,
549 .unbind_channel = NULL,
550 .max_entries = NULL,
551 },
552#endif /* CONFIG_GK20A_CTXSW_TRACE */
553 .mm = {
554 .support_sparse = gm20b_mm_support_sparse,
555 .gmmu_map = gk20a_locked_gmmu_map,
556 .gmmu_unmap = gk20a_locked_gmmu_unmap,
557 .vm_bind_channel = gk20a_vm_bind_channel,
558 .fb_flush = gk20a_mm_fb_flush,
559 .l2_invalidate = gk20a_mm_l2_invalidate,
560 .l2_flush = gv11b_mm_l2_flush,
561 .cbc_clean = gk20a_mm_cbc_clean,
562 .set_big_page_size = gm20b_mm_set_big_page_size,
563 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
564 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
565 .gpu_phys_addr = gv11b_gpu_phys_addr,
566 .get_iommu_bit = gp10b_mm_get_iommu_bit,
567 .get_mmu_levels = gp10b_mm_get_mmu_levels,
568 .init_pdb = gp10b_mm_init_pdb,
569 .init_mm_setup_hw = gv11b_init_mm_setup_hw,
570 .is_bar1_supported = gv11b_mm_is_bar1_supported,
571 .alloc_inst_block = gk20a_alloc_inst_block,
572 .init_inst_block = gv11b_init_inst_block,
573 .mmu_fault_pending = gv11b_mm_mmu_fault_pending,
574 .get_kind_invalid = gm20b_get_kind_invalid,
575 .get_kind_pitch = gm20b_get_kind_pitch,
576 .init_bar2_vm = gb10b_init_bar2_vm,
577 .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup,
578 .remove_bar2_vm = gv11b_mm_remove_bar2_vm,
579 .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy,
580 },
581 .therm = {
582 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
583 .elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
584 },
585 .pmu = {
586 .pmu_setup_elpg = gp10b_pmu_setup_elpg,
587 .pmu_get_queue_head = pwr_pmu_queue_head_r,
588 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
589 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
590 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
591 .pmu_queue_head = gk20a_pmu_queue_head,
592 .pmu_queue_tail = gk20a_pmu_queue_tail,
593 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
594 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
595 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
596 .pmu_mutex_release = gk20a_pmu_mutex_release,
597 .write_dmatrfbase = gp10b_write_dmatrfbase,
598 .pmu_elpg_statistics = gp106_pmu_elpg_statistics,
599 .pmu_pg_init_param = gv11b_pg_gr_init,
600 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
601 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
602 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
603 .reset_engine = gp106_pmu_engine_reset,
604 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
605 .pmu_nsbootstrap = gv11b_pmu_bootstrap,
606 .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask,
607 .is_pmu_supported = gv11b_is_pmu_supported,
608 },
609 .regops = {
610 .get_global_whitelist_ranges =
611 gv11b_get_global_whitelist_ranges,
612 .get_global_whitelist_ranges_count =
613 gv11b_get_global_whitelist_ranges_count,
614 .get_context_whitelist_ranges =
615 gv11b_get_context_whitelist_ranges,
616 .get_context_whitelist_ranges_count =
617 gv11b_get_context_whitelist_ranges_count,
618 .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist,
619 .get_runcontrol_whitelist_count =
620 gv11b_get_runcontrol_whitelist_count,
621 .get_runcontrol_whitelist_ranges =
622 gv11b_get_runcontrol_whitelist_ranges,
623 .get_runcontrol_whitelist_ranges_count =
624 gv11b_get_runcontrol_whitelist_ranges_count,
625 .get_qctl_whitelist = gv11b_get_qctl_whitelist,
626 .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count,
627 .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges,
628 .get_qctl_whitelist_ranges_count =
629 gv11b_get_qctl_whitelist_ranges_count,
630 .apply_smpc_war = gv11b_apply_smpc_war,
631 },
632 .mc = {
633 .intr_enable = mc_gv11b_intr_enable,
634 .intr_unit_config = mc_gp10b_intr_unit_config,
635 .isr_stall = mc_gp10b_isr_stall,
636 .intr_stall = mc_gp10b_intr_stall,
637 .intr_stall_pause = mc_gp10b_intr_stall_pause,
638 .intr_stall_resume = mc_gp10b_intr_stall_resume,
639 .intr_nonstall = mc_gp10b_intr_nonstall,
640 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
641 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
642 .enable = gk20a_mc_enable,
643 .disable = gk20a_mc_disable,
644 .reset = gk20a_mc_reset,
645 .boot_0 = gk20a_mc_boot_0,
646 .is_intr1_pending = mc_gp10b_is_intr1_pending,
647 .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
648 },
649 .debug = {
650 .show_dump = gk20a_debug_show_dump,
651 },
652 .dbg_session_ops = {
653 .exec_reg_ops = exec_regops_gk20a,
654 .dbg_set_powergate = dbg_set_powergate,
655 .check_and_set_global_reservation =
656 nvgpu_check_and_set_global_reservation,
657 .check_and_set_context_reservation =
658 nvgpu_check_and_set_context_reservation,
659 .release_profiler_reservation =
660 nvgpu_release_profiler_reservation,
661 .perfbuffer_enable = gv11b_perfbuf_enable_locked,
662 .perfbuffer_disable = gv11b_perfbuf_disable_locked,
663 },
664 .bus = {
665 .init_hw = gk20a_bus_init_hw,
666 .isr = gk20a_bus_isr,
667 .read_ptimer = gk20a_read_ptimer,
668 .get_timestamps_zipper = nvgpu_get_timestamps_zipper,
669 .bar1_bind = NULL,
670 },
671#if defined(CONFIG_GK20A_CYCLE_STATS)
672 .css = {
673 .enable_snapshot = gv11b_css_hw_enable_snapshot,
674 .disable_snapshot = gv11b_css_hw_disable_snapshot,
675 .check_data_available = gv11b_css_hw_check_data_available,
676 .set_handled_snapshots = css_hw_set_handled_snapshots,
677 .allocate_perfmon_ids = css_gr_allocate_perfmon_ids,
678 .release_perfmon_ids = css_gr_release_perfmon_ids,
679 },
680#endif
681 .falcon = {
682 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
683 },
684 .priv_ring = {
685 .isr = gp10b_priv_ring_isr,
686 },
687 .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics,
688 .get_litter_value = gv11b_get_litter_value,
689};
690
691int gv11b_init_hal(struct gk20a *g)
692{
693 struct gpu_ops *gops = &g->ops;
694 u32 val;
695 bool priv_security;
696
697 gops->ltc = gv11b_ops.ltc;
698 gops->ce2 = gv11b_ops.ce2;
699 gops->gr = gv11b_ops.gr;
700 gops->fb = gv11b_ops.fb;
701 gops->clock_gating = gv11b_ops.clock_gating;
702 gops->fifo = gv11b_ops.fifo;
703 gops->gr_ctx = gv11b_ops.gr_ctx;
704 gops->mm = gv11b_ops.mm;
705#ifdef CONFIG_GK20A_CTXSW_TRACE
706 gops->fecs_trace = gv11b_ops.fecs_trace;
707#endif
708 gops->therm = gv11b_ops.therm;
709 gops->pmu = gv11b_ops.pmu;
710 gops->regops = gv11b_ops.regops;
711 gops->mc = gv11b_ops.mc;
712 gops->debug = gv11b_ops.debug;
713 gops->dbg_session_ops = gv11b_ops.dbg_session_ops;
714 gops->bus = gv11b_ops.bus;
715#if defined(CONFIG_GK20A_CYCLE_STATS)
716 gops->css = gv11b_ops.css;
717#endif
718 gops->falcon = gv11b_ops.falcon;
719 gops->priv_ring = gv11b_ops.priv_ring;
720
721 /* Lone functions */
722 gops->chip_init_gpu_characteristics =
723 gv11b_ops.chip_init_gpu_characteristics;
724 gops->get_litter_value = gv11b_ops.get_litter_value;
725
726 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
727 if (val) {
728 priv_security = true;
729 pr_err("priv security is enabled\n");
730 } else {
731 priv_security = false;
732 pr_err("priv security is disabled\n");
733 }
734 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);
735 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security);
736 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security);
737
738 /* priv security dependent ops */
739 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
740 /* Add in ops from gm20b acr */
741 gops->pmu.prepare_ucode = gp106_prepare_ucode_blob,
742 gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn,
743 gops->pmu.get_wpr = gm20b_wpr_info,
744 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
745 gops->pmu.pmu_populate_loader_cfg =
746 gp106_pmu_populate_loader_cfg,
747 gops->pmu.flcn_populate_bl_dmem_desc =
748 gp106_flcn_populate_bl_dmem_desc,
749 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
750 gops->pmu.falcon_clear_halt_interrupt_status =
751 clear_halt_interrupt_status,
752 gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1,
753
754 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
755 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
756 gops->pmu.is_lazy_bootstrap = gv11b_is_lazy_bootstrap,
757 gops->pmu.is_priv_load = gv11b_is_priv_load,
758
759 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
760 } else {
761 /* Inherit from gk20a */
762 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
763 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
764
765 gops->pmu.load_lsfalcon_ucode = NULL;
766 gops->pmu.init_wpr_region = NULL;
767 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
768
769 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
770 }
771
772 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
773 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
774
775 g->name = "gv11b";
776
777 return 0;
778}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-15 23:56:52 -0400