diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c | 750 |
1 files changed, 0 insertions, 750 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c deleted file mode 100644 index 4dbc87d5..00000000 --- a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c +++ /dev/null | |||
@@ -1,750 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * This file is autogenerated. Do not edit. | ||
23 | */ | ||
24 | |||
25 | #ifndef __gv11b_gating_reglist_h__ | ||
26 | #define __gv11b_gating_reglist_h__ | ||
27 | |||
28 | #include <linux/types.h> | ||
29 | #include "gv11b_gating_reglist.h" | ||
30 | #include <nvgpu/enabled.h> | ||
31 | |||
32 | struct gating_desc { | ||
33 | u32 addr; | ||
34 | u32 prod; | ||
35 | u32 disable; | ||
36 | }; | ||
37 | /* slcg bus */ | ||
38 | static const struct gating_desc gv11b_slcg_bus[] = { | ||
39 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | ||
40 | }; | ||
41 | |||
42 | /* slcg ce2 */ | ||
43 | static const struct gating_desc gv11b_slcg_ce2[] = { | ||
44 | {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, | ||
45 | }; | ||
46 | |||
47 | /* slcg chiplet */ | ||
48 | static const struct gating_desc gv11b_slcg_chiplet[] = { | ||
49 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
50 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
51 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
52 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
53 | }; | ||
54 | |||
55 | /* slcg fb */ | ||
56 | static const struct gating_desc gv11b_slcg_fb[] = { | ||
57 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
58 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
59 | }; | ||
60 | |||
61 | /* slcg fifo */ | ||
62 | static const struct gating_desc gv11b_slcg_fifo[] = { | ||
63 | {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
64 | }; | ||
65 | |||
66 | /* slcg gr */ | ||
67 | static const struct gating_desc gv11b_slcg_gr[] = { | ||
68 | {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, | ||
69 | {.addr = 0x00409134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
70 | {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, | ||
71 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
72 | {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, | ||
73 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | ||
74 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
75 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | ||
76 | /* fix priv error */ | ||
77 | /*{.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},*/ | ||
78 | /*{.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002},*/ | ||
79 | {.addr = 0x0041a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
80 | {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, | ||
81 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | ||
82 | /* fix priv error */ | ||
83 | /*{.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},*/ | ||
84 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | ||
85 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, | ||
86 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | ||
87 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
88 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | ||
89 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
90 | /* fix priv error */ | ||
91 | /*{.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe},*/ | ||
92 | {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
93 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
94 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
95 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
96 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | ||
97 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
98 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, | ||
99 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | ||
100 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | ||
101 | {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, | ||
102 | {.addr = 0x00419c94, .prod = 0x00080040, .disable = 0x000ffffe}, | ||
103 | {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, | ||
104 | {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, | ||
105 | {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, | ||
106 | {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, | ||
107 | {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, | ||
108 | {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, | ||
109 | {.addr = 0x00419a64, .prod = 0x000001ba, .disable = 0x000001fe}, | ||
110 | {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, | ||
111 | {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, | ||
112 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
113 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
114 | /* fix priv error */ | ||
115 | /*{.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},*/ | ||
116 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
117 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
118 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
119 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, | ||
120 | }; | ||
121 | |||
122 | /* slcg ltc */ | ||
123 | static const struct gating_desc gv11b_slcg_ltc[] = { | ||
124 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
125 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
126 | }; | ||
127 | |||
128 | /* slcg perf */ | ||
129 | static const struct gating_desc gv11b_slcg_perf[] = { | ||
130 | {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
131 | {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
132 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
133 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
134 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
135 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
136 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
137 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
138 | {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, | ||
139 | }; | ||
140 | |||
141 | /* slcg PriRing */ | ||
142 | static const struct gating_desc gv11b_slcg_priring[] = { | ||
143 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | ||
144 | }; | ||
145 | |||
146 | /* slcg pwr_csb */ | ||
147 | static const struct gating_desc gv11b_slcg_pwr_csb[] = { | ||
148 | {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
149 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
150 | {.addr = 0x00000a74, .prod = 0x00004040, .disable = 0x00007ffe}, | ||
151 | {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, | ||
152 | }; | ||
153 | |||
154 | /* slcg pmu */ | ||
155 | static const struct gating_desc gv11b_slcg_pmu[] = { | ||
156 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
157 | {.addr = 0x0010aa74, .prod = 0x00004040, .disable = 0x00007ffe}, | ||
158 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
159 | }; | ||
160 | |||
161 | /* therm gr */ | ||
162 | static const struct gating_desc gv11b_slcg_therm[] = { | ||
163 | {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, | ||
164 | }; | ||
165 | |||
166 | /* slcg Xbar */ | ||
167 | static const struct gating_desc gv11b_slcg_xbar[] = { | ||
168 | {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
169 | {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
170 | {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
171 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
172 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
173 | }; | ||
174 | |||
175 | /* blcg bus */ | ||
176 | static const struct gating_desc gv11b_blcg_bus[] = { | ||
177 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | ||
178 | }; | ||
179 | |||
180 | /* blcg ce */ | ||
181 | static const struct gating_desc gv11b_blcg_ce[] = { | ||
182 | {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, | ||
183 | }; | ||
184 | |||
185 | /* blcg ctxsw prog */ | ||
186 | static const struct gating_desc gv11b_blcg_ctxsw_prog[] = { | ||
187 | }; | ||
188 | |||
189 | /* blcg fb */ | ||
190 | static const struct gating_desc gv11b_blcg_fb[] = { | ||
191 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
192 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | ||
193 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | ||
194 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
195 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | ||
196 | }; | ||
197 | |||
198 | /* blcg fifo */ | ||
199 | static const struct gating_desc gv11b_blcg_fifo[] = { | ||
200 | {.addr = 0x000026e0, .prod = 0x0000c244, .disable = 0x00000000}, | ||
201 | }; | ||
202 | |||
203 | /* blcg gr */ | ||
204 | static const struct gating_desc gv11b_blcg_gr[] = { | ||
205 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | ||
206 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
207 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
208 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | ||
209 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | ||
210 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | ||
211 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
212 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | ||
213 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | ||
214 | {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
215 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | ||
216 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
217 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | ||
218 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | ||
219 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | ||
220 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | ||
221 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | ||
222 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | ||
223 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | ||
224 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
225 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
226 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
227 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
228 | {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
229 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | ||
230 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | ||
231 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | ||
232 | {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, | ||
233 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
234 | {.addr = 0x00419c80, .prod = 0x00004045, .disable = 0x00000000}, | ||
235 | {.addr = 0x00419c88, .prod = 0x00004043, .disable = 0x00000000}, | ||
236 | {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, | ||
237 | {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, | ||
238 | {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, | ||
239 | {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, | ||
240 | {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, | ||
241 | {.addr = 0x00419a40, .prod = 0x00000242, .disable = 0x00000000}, | ||
242 | {.addr = 0x00419a48, .prod = 0x00000242, .disable = 0x00000000}, | ||
243 | {.addr = 0x00419a50, .prod = 0x00000242, .disable = 0x00000000}, | ||
244 | {.addr = 0x00419a58, .prod = 0x00000242, .disable = 0x00000000}, | ||
245 | {.addr = 0x00419a60, .prod = 0x00000202, .disable = 0x00000000}, | ||
246 | {.addr = 0x00419a68, .prod = 0x00000202, .disable = 0x00000000}, | ||
247 | {.addr = 0x00419a78, .prod = 0x00000242, .disable = 0x00000000}, | ||
248 | {.addr = 0x00419a80, .prod = 0x00000242, .disable = 0x00000000}, | ||
249 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | ||
250 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | ||
251 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
252 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | ||
253 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
254 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
255 | }; | ||
256 | |||
257 | /* blcg ltc */ | ||
258 | static const struct gating_desc gv11b_blcg_ltc[] = { | ||
259 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | ||
260 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | ||
261 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
262 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
263 | }; | ||
264 | |||
265 | /* blcg pwr_csb */ | ||
266 | static const struct gating_desc gv11b_blcg_pwr_csb[] = { | ||
267 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | ||
268 | }; | ||
269 | |||
270 | /* blcg pmu */ | ||
271 | static const struct gating_desc gv11b_blcg_pmu[] = { | ||
272 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | ||
273 | }; | ||
274 | |||
275 | /* blcg Xbar */ | ||
276 | static const struct gating_desc gv11b_blcg_xbar[] = { | ||
277 | {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, | ||
278 | {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, | ||
279 | {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, | ||
280 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | ||
281 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | ||
282 | }; | ||
283 | |||
284 | /* pg gr */ | ||
285 | static const struct gating_desc gv11b_pg_gr[] = { | ||
286 | }; | ||
287 | |||
288 | /* inline functions */ | ||
289 | void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, | ||
290 | bool prod) | ||
291 | { | ||
292 | u32 i; | ||
293 | u32 size = sizeof(gv11b_slcg_bus) / sizeof(struct gating_desc); | ||
294 | |||
295 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
296 | return; | ||
297 | |||
298 | for (i = 0; i < size; i++) { | ||
299 | if (prod) | ||
300 | gk20a_writel(g, gv11b_slcg_bus[i].addr, | ||
301 | gv11b_slcg_bus[i].prod); | ||
302 | else | ||
303 | gk20a_writel(g, gv11b_slcg_bus[i].addr, | ||
304 | gv11b_slcg_bus[i].disable); | ||
305 | } | ||
306 | } | ||
307 | |||
308 | void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
309 | bool prod) | ||
310 | { | ||
311 | u32 i; | ||
312 | u32 size = sizeof(gv11b_slcg_ce2) / sizeof(struct gating_desc); | ||
313 | |||
314 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
315 | return; | ||
316 | |||
317 | for (i = 0; i < size; i++) { | ||
318 | if (prod) | ||
319 | gk20a_writel(g, gv11b_slcg_ce2[i].addr, | ||
320 | gv11b_slcg_ce2[i].prod); | ||
321 | else | ||
322 | gk20a_writel(g, gv11b_slcg_ce2[i].addr, | ||
323 | gv11b_slcg_ce2[i].disable); | ||
324 | } | ||
325 | } | ||
326 | |||
327 | void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
328 | bool prod) | ||
329 | { | ||
330 | u32 i; | ||
331 | u32 size = sizeof(gv11b_slcg_chiplet) / sizeof(struct gating_desc); | ||
332 | |||
333 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
334 | return; | ||
335 | |||
336 | for (i = 0; i < size; i++) { | ||
337 | if (prod) | ||
338 | gk20a_writel(g, gv11b_slcg_chiplet[i].addr, | ||
339 | gv11b_slcg_chiplet[i].prod); | ||
340 | else | ||
341 | gk20a_writel(g, gv11b_slcg_chiplet[i].addr, | ||
342 | gv11b_slcg_chiplet[i].disable); | ||
343 | } | ||
344 | } | ||
345 | |||
346 | void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
347 | bool prod) | ||
348 | { | ||
349 | } | ||
350 | |||
351 | void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, | ||
352 | bool prod) | ||
353 | { | ||
354 | u32 i; | ||
355 | u32 size = sizeof(gv11b_slcg_fb) / sizeof(struct gating_desc); | ||
356 | |||
357 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
358 | return; | ||
359 | |||
360 | for (i = 0; i < size; i++) { | ||
361 | if (prod) | ||
362 | gk20a_writel(g, gv11b_slcg_fb[i].addr, | ||
363 | gv11b_slcg_fb[i].prod); | ||
364 | else | ||
365 | gk20a_writel(g, gv11b_slcg_fb[i].addr, | ||
366 | gv11b_slcg_fb[i].disable); | ||
367 | } | ||
368 | } | ||
369 | |||
370 | void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
371 | bool prod) | ||
372 | { | ||
373 | u32 i; | ||
374 | u32 size = sizeof(gv11b_slcg_fifo) / sizeof(struct gating_desc); | ||
375 | |||
376 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
377 | return; | ||
378 | |||
379 | for (i = 0; i < size; i++) { | ||
380 | if (prod) | ||
381 | gk20a_writel(g, gv11b_slcg_fifo[i].addr, | ||
382 | gv11b_slcg_fifo[i].prod); | ||
383 | else | ||
384 | gk20a_writel(g, gv11b_slcg_fifo[i].addr, | ||
385 | gv11b_slcg_fifo[i].disable); | ||
386 | } | ||
387 | } | ||
388 | |||
389 | void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
390 | bool prod) | ||
391 | { | ||
392 | u32 i; | ||
393 | u32 size = sizeof(gv11b_slcg_gr) / sizeof(struct gating_desc); | ||
394 | |||
395 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
396 | return; | ||
397 | |||
398 | for (i = 0; i < size; i++) { | ||
399 | if (prod) | ||
400 | gk20a_writel(g, gv11b_slcg_gr[i].addr, | ||
401 | gv11b_slcg_gr[i].prod); | ||
402 | else | ||
403 | gk20a_writel(g, gv11b_slcg_gr[i].addr, | ||
404 | gv11b_slcg_gr[i].disable); | ||
405 | } | ||
406 | } | ||
407 | |||
408 | void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
409 | bool prod) | ||
410 | { | ||
411 | u32 i; | ||
412 | u32 size = sizeof(gv11b_slcg_ltc) / sizeof(struct gating_desc); | ||
413 | |||
414 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
415 | return; | ||
416 | |||
417 | for (i = 0; i < size; i++) { | ||
418 | if (prod) | ||
419 | gk20a_writel(g, gv11b_slcg_ltc[i].addr, | ||
420 | gv11b_slcg_ltc[i].prod); | ||
421 | else | ||
422 | gk20a_writel(g, gv11b_slcg_ltc[i].addr, | ||
423 | gv11b_slcg_ltc[i].disable); | ||
424 | } | ||
425 | } | ||
426 | |||
427 | void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
428 | bool prod) | ||
429 | { | ||
430 | u32 i; | ||
431 | u32 size = sizeof(gv11b_slcg_perf) / sizeof(struct gating_desc); | ||
432 | |||
433 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
434 | return; | ||
435 | |||
436 | for (i = 0; i < size; i++) { | ||
437 | if (prod) | ||
438 | gk20a_writel(g, gv11b_slcg_perf[i].addr, | ||
439 | gv11b_slcg_perf[i].prod); | ||
440 | else | ||
441 | gk20a_writel(g, gv11b_slcg_perf[i].addr, | ||
442 | gv11b_slcg_perf[i].disable); | ||
443 | } | ||
444 | } | ||
445 | |||
446 | void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, | ||
447 | bool prod) | ||
448 | { | ||
449 | u32 i; | ||
450 | u32 size = sizeof(gv11b_slcg_priring) / sizeof(struct gating_desc); | ||
451 | |||
452 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
453 | return; | ||
454 | |||
455 | for (i = 0; i < size; i++) { | ||
456 | if (prod) | ||
457 | gk20a_writel(g, gv11b_slcg_priring[i].addr, | ||
458 | gv11b_slcg_priring[i].prod); | ||
459 | else | ||
460 | gk20a_writel(g, gv11b_slcg_priring[i].addr, | ||
461 | gv11b_slcg_priring[i].disable); | ||
462 | } | ||
463 | } | ||
464 | |||
465 | void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
466 | bool prod) | ||
467 | { | ||
468 | u32 i; | ||
469 | u32 size = sizeof(gv11b_slcg_pwr_csb) / sizeof(struct gating_desc); | ||
470 | |||
471 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
472 | return; | ||
473 | |||
474 | for (i = 0; i < size; i++) { | ||
475 | if (prod) | ||
476 | gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, | ||
477 | gv11b_slcg_pwr_csb[i].prod); | ||
478 | else | ||
479 | gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, | ||
480 | gv11b_slcg_pwr_csb[i].disable); | ||
481 | } | ||
482 | } | ||
483 | |||
484 | void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
485 | bool prod) | ||
486 | { | ||
487 | u32 i; | ||
488 | u32 size = sizeof(gv11b_slcg_pmu) / sizeof(struct gating_desc); | ||
489 | |||
490 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
491 | return; | ||
492 | |||
493 | for (i = 0; i < size; i++) { | ||
494 | if (prod) | ||
495 | gk20a_writel(g, gv11b_slcg_pmu[i].addr, | ||
496 | gv11b_slcg_pmu[i].prod); | ||
497 | else | ||
498 | gk20a_writel(g, gv11b_slcg_pmu[i].addr, | ||
499 | gv11b_slcg_pmu[i].disable); | ||
500 | } | ||
501 | } | ||
502 | |||
503 | void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
504 | bool prod) | ||
505 | { | ||
506 | u32 i; | ||
507 | u32 size = sizeof(gv11b_slcg_therm) / sizeof(struct gating_desc); | ||
508 | |||
509 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
510 | return; | ||
511 | |||
512 | for (i = 0; i < size; i++) { | ||
513 | if (prod) | ||
514 | gk20a_writel(g, gv11b_slcg_therm[i].addr, | ||
515 | gv11b_slcg_therm[i].prod); | ||
516 | else | ||
517 | gk20a_writel(g, gv11b_slcg_therm[i].addr, | ||
518 | gv11b_slcg_therm[i].disable); | ||
519 | } | ||
520 | } | ||
521 | |||
522 | void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
523 | bool prod) | ||
524 | { | ||
525 | u32 i; | ||
526 | u32 size = sizeof(gv11b_slcg_xbar) / sizeof(struct gating_desc); | ||
527 | |||
528 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
529 | return; | ||
530 | |||
531 | for (i = 0; i < size; i++) { | ||
532 | if (prod) | ||
533 | gk20a_writel(g, gv11b_slcg_xbar[i].addr, | ||
534 | gv11b_slcg_xbar[i].prod); | ||
535 | else | ||
536 | gk20a_writel(g, gv11b_slcg_xbar[i].addr, | ||
537 | gv11b_slcg_xbar[i].disable); | ||
538 | } | ||
539 | } | ||
540 | |||
541 | void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, | ||
542 | bool prod) | ||
543 | { | ||
544 | u32 i; | ||
545 | u32 size = sizeof(gv11b_blcg_bus) / sizeof(struct gating_desc); | ||
546 | |||
547 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
548 | return; | ||
549 | |||
550 | for (i = 0; i < size; i++) { | ||
551 | if (prod) | ||
552 | gk20a_writel(g, gv11b_blcg_bus[i].addr, | ||
553 | gv11b_blcg_bus[i].prod); | ||
554 | else | ||
555 | gk20a_writel(g, gv11b_blcg_bus[i].addr, | ||
556 | gv11b_blcg_bus[i].disable); | ||
557 | } | ||
558 | } | ||
559 | |||
560 | void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, | ||
561 | bool prod) | ||
562 | { | ||
563 | u32 i; | ||
564 | u32 size = sizeof(gv11b_blcg_ce) / sizeof(struct gating_desc); | ||
565 | |||
566 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
567 | return; | ||
568 | |||
569 | for (i = 0; i < size; i++) { | ||
570 | if (prod) | ||
571 | gk20a_writel(g, gv11b_blcg_ce[i].addr, | ||
572 | gv11b_blcg_ce[i].prod); | ||
573 | else | ||
574 | gk20a_writel(g, gv11b_blcg_ce[i].addr, | ||
575 | gv11b_blcg_ce[i].disable); | ||
576 | } | ||
577 | } | ||
578 | |||
579 | void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
580 | bool prod) | ||
581 | { | ||
582 | u32 i; | ||
583 | u32 size = sizeof(gv11b_blcg_ctxsw_prog) / sizeof(struct gating_desc); | ||
584 | |||
585 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
586 | return; | ||
587 | |||
588 | for (i = 0; i < size; i++) { | ||
589 | if (prod) | ||
590 | gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, | ||
591 | gv11b_blcg_ctxsw_prog[i].prod); | ||
592 | else | ||
593 | gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, | ||
594 | gv11b_blcg_ctxsw_prog[i].disable); | ||
595 | } | ||
596 | } | ||
597 | |||
598 | void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, | ||
599 | bool prod) | ||
600 | { | ||
601 | u32 i; | ||
602 | u32 size = sizeof(gv11b_blcg_fb) / sizeof(struct gating_desc); | ||
603 | |||
604 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
605 | return; | ||
606 | |||
607 | for (i = 0; i < size; i++) { | ||
608 | if (prod) | ||
609 | gk20a_writel(g, gv11b_blcg_fb[i].addr, | ||
610 | gv11b_blcg_fb[i].prod); | ||
611 | else | ||
612 | gk20a_writel(g, gv11b_blcg_fb[i].addr, | ||
613 | gv11b_blcg_fb[i].disable); | ||
614 | } | ||
615 | } | ||
616 | |||
617 | void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
618 | bool prod) | ||
619 | { | ||
620 | u32 i; | ||
621 | u32 size = sizeof(gv11b_blcg_fifo) / sizeof(struct gating_desc); | ||
622 | |||
623 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
624 | return; | ||
625 | |||
626 | for (i = 0; i < size; i++) { | ||
627 | if (prod) | ||
628 | gk20a_writel(g, gv11b_blcg_fifo[i].addr, | ||
629 | gv11b_blcg_fifo[i].prod); | ||
630 | else | ||
631 | gk20a_writel(g, gv11b_blcg_fifo[i].addr, | ||
632 | gv11b_blcg_fifo[i].disable); | ||
633 | } | ||
634 | } | ||
635 | |||
636 | void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
637 | bool prod) | ||
638 | { | ||
639 | u32 i; | ||
640 | u32 size = sizeof(gv11b_blcg_gr) / sizeof(struct gating_desc); | ||
641 | |||
642 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
643 | return; | ||
644 | |||
645 | for (i = 0; i < size; i++) { | ||
646 | if (prod) | ||
647 | gk20a_writel(g, gv11b_blcg_gr[i].addr, | ||
648 | gv11b_blcg_gr[i].prod); | ||
649 | else | ||
650 | gk20a_writel(g, gv11b_blcg_gr[i].addr, | ||
651 | gv11b_blcg_gr[i].disable); | ||
652 | } | ||
653 | } | ||
654 | |||
655 | void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
656 | bool prod) | ||
657 | { | ||
658 | u32 i; | ||
659 | u32 size = sizeof(gv11b_blcg_ltc) / sizeof(struct gating_desc); | ||
660 | |||
661 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
662 | return; | ||
663 | |||
664 | for (i = 0; i < size; i++) { | ||
665 | if (prod) | ||
666 | gk20a_writel(g, gv11b_blcg_ltc[i].addr, | ||
667 | gv11b_blcg_ltc[i].prod); | ||
668 | else | ||
669 | gk20a_writel(g, gv11b_blcg_ltc[i].addr, | ||
670 | gv11b_blcg_ltc[i].disable); | ||
671 | } | ||
672 | } | ||
673 | |||
674 | void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
675 | bool prod) | ||
676 | { | ||
677 | u32 i; | ||
678 | u32 size = sizeof(gv11b_blcg_pwr_csb) / sizeof(struct gating_desc); | ||
679 | |||
680 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
681 | return; | ||
682 | |||
683 | for (i = 0; i < size; i++) { | ||
684 | if (prod) | ||
685 | gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, | ||
686 | gv11b_blcg_pwr_csb[i].prod); | ||
687 | else | ||
688 | gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, | ||
689 | gv11b_blcg_pwr_csb[i].disable); | ||
690 | } | ||
691 | } | ||
692 | |||
693 | void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
694 | bool prod) | ||
695 | { | ||
696 | u32 i; | ||
697 | u32 size = sizeof(gv11b_blcg_pmu) / sizeof(struct gating_desc); | ||
698 | |||
699 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
700 | return; | ||
701 | |||
702 | for (i = 0; i < size; i++) { | ||
703 | if (prod) | ||
704 | gk20a_writel(g, gv11b_blcg_pmu[i].addr, | ||
705 | gv11b_blcg_pmu[i].prod); | ||
706 | else | ||
707 | gk20a_writel(g, gv11b_blcg_pmu[i].addr, | ||
708 | gv11b_blcg_pmu[i].disable); | ||
709 | } | ||
710 | } | ||
711 | |||
712 | void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
713 | bool prod) | ||
714 | { | ||
715 | u32 i; | ||
716 | u32 size = sizeof(gv11b_blcg_xbar) / sizeof(struct gating_desc); | ||
717 | |||
718 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
719 | return; | ||
720 | |||
721 | for (i = 0; i < size; i++) { | ||
722 | if (prod) | ||
723 | gk20a_writel(g, gv11b_blcg_xbar[i].addr, | ||
724 | gv11b_blcg_xbar[i].prod); | ||
725 | else | ||
726 | gk20a_writel(g, gv11b_blcg_xbar[i].addr, | ||
727 | gv11b_blcg_xbar[i].disable); | ||
728 | } | ||
729 | } | ||
730 | |||
731 | void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, | ||
732 | bool prod) | ||
733 | { | ||
734 | u32 i; | ||
735 | u32 size = sizeof(gv11b_pg_gr) / sizeof(struct gating_desc); | ||
736 | |||
737 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
738 | return; | ||
739 | |||
740 | for (i = 0; i < size; i++) { | ||
741 | if (prod) | ||
742 | gk20a_writel(g, gv11b_pg_gr[i].addr, | ||
743 | gv11b_pg_gr[i].prod); | ||
744 | else | ||
745 | gk20a_writel(g, gv11b_pg_gr[i].addr, | ||
746 | gv11b_pg_gr[i].disable); | ||
747 | } | ||
748 | } | ||
749 | |||
750 | #endif /* __gv11b_gating_reglist_h__ */ | ||