diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c | 748 |
1 files changed, 748 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c new file mode 100644 index 00000000..9f6057ae --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c | |||
@@ -0,0 +1,748 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * This file is autogenerated. Do not edit. | ||
23 | */ | ||
24 | |||
25 | #ifndef __gv11b_gating_reglist_h__ | ||
26 | #define __gv11b_gating_reglist_h__ | ||
27 | |||
28 | #include <linux/types.h> | ||
29 | #include "gv11b_gating_reglist.h" | ||
30 | #include <nvgpu/enabled.h> | ||
31 | |||
32 | struct gating_desc { | ||
33 | u32 addr; | ||
34 | u32 prod; | ||
35 | u32 disable; | ||
36 | }; | ||
37 | /* slcg bus */ | ||
38 | static const struct gating_desc gv11b_slcg_bus[] = { | ||
39 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | ||
40 | }; | ||
41 | |||
42 | /* slcg ce2 */ | ||
43 | static const struct gating_desc gv11b_slcg_ce2[] = { | ||
44 | {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, | ||
45 | }; | ||
46 | |||
47 | /* slcg chiplet */ | ||
48 | static const struct gating_desc gv11b_slcg_chiplet[] = { | ||
49 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
50 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
51 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
52 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
53 | }; | ||
54 | |||
55 | /* slcg fb */ | ||
56 | static const struct gating_desc gv11b_slcg_fb[] = { | ||
57 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
58 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
59 | }; | ||
60 | |||
61 | /* slcg fifo */ | ||
62 | static const struct gating_desc gv11b_slcg_fifo[] = { | ||
63 | {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
64 | }; | ||
65 | |||
66 | /* slcg gr */ | ||
67 | static const struct gating_desc gv11b_slcg_gr[] = { | ||
68 | {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, | ||
69 | {.addr = 0x00409134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
70 | {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, | ||
71 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
72 | {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, | ||
73 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | ||
74 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
75 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | ||
76 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, | ||
77 | {.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002}, | ||
78 | {.addr = 0x0041a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
79 | {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, | ||
80 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | ||
81 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
82 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | ||
83 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, | ||
84 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | ||
85 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
86 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | ||
87 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
88 | {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, | ||
89 | {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
90 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
91 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
92 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
93 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | ||
94 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
95 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, | ||
96 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | ||
97 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | ||
98 | {.addr = 0x00419c84, .prod = 0x0003fff8, .disable = 0x0003fffe}, | ||
99 | {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, | ||
100 | {.addr = 0x00419c94, .prod = 0x00080040, .disable = 0x000ffffe}, | ||
101 | {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, | ||
102 | {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, | ||
103 | {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, | ||
104 | {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, | ||
105 | {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, | ||
106 | {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, | ||
107 | {.addr = 0x00419a64, .prod = 0x000001ba, .disable = 0x000001fe}, | ||
108 | {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, | ||
109 | {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, | ||
110 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
111 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
112 | {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
113 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
114 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
115 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
116 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, | ||
117 | }; | ||
118 | |||
119 | /* slcg ltc */ | ||
120 | static const struct gating_desc gv11b_slcg_ltc[] = { | ||
121 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
122 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
123 | }; | ||
124 | |||
125 | /* slcg perf */ | ||
126 | static const struct gating_desc gv11b_slcg_perf[] = { | ||
127 | {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
128 | {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
129 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
130 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
131 | {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
132 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
133 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
134 | {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, | ||
135 | {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, | ||
136 | }; | ||
137 | |||
138 | /* slcg PriRing */ | ||
139 | static const struct gating_desc gv11b_slcg_priring[] = { | ||
140 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | ||
141 | }; | ||
142 | |||
143 | /* slcg pwr_csb */ | ||
144 | static const struct gating_desc gv11b_slcg_pwr_csb[] = { | ||
145 | {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
146 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
147 | {.addr = 0x00000a74, .prod = 0x00004040, .disable = 0x00007ffe}, | ||
148 | {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, | ||
149 | }; | ||
150 | |||
151 | /* slcg pmu */ | ||
152 | static const struct gating_desc gv11b_slcg_pmu[] = { | ||
153 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
154 | {.addr = 0x0010aa74, .prod = 0x00004040, .disable = 0x00007ffe}, | ||
155 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
156 | }; | ||
157 | |||
158 | /* therm gr */ | ||
159 | static const struct gating_desc gv11b_slcg_therm[] = { | ||
160 | {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, | ||
161 | }; | ||
162 | |||
163 | /* slcg Xbar */ | ||
164 | static const struct gating_desc gv11b_slcg_xbar[] = { | ||
165 | {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
166 | {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
167 | {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
168 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
169 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
170 | }; | ||
171 | |||
172 | /* blcg bus */ | ||
173 | static const struct gating_desc gv11b_blcg_bus[] = { | ||
174 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | ||
175 | }; | ||
176 | |||
177 | /* blcg ce */ | ||
178 | static const struct gating_desc gv11b_blcg_ce[] = { | ||
179 | {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, | ||
180 | }; | ||
181 | |||
182 | /* blcg ctxsw prog */ | ||
183 | static const struct gating_desc gv11b_blcg_ctxsw_prog[] = { | ||
184 | }; | ||
185 | |||
186 | /* blcg fb */ | ||
187 | static const struct gating_desc gv11b_blcg_fb[] = { | ||
188 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
189 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | ||
190 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | ||
191 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
192 | {.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000}, | ||
193 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | ||
194 | }; | ||
195 | |||
196 | /* blcg fifo */ | ||
197 | static const struct gating_desc gv11b_blcg_fifo[] = { | ||
198 | {.addr = 0x000026e0, .prod = 0x0000c244, .disable = 0x00000000}, | ||
199 | }; | ||
200 | |||
201 | /* blcg gr */ | ||
202 | static const struct gating_desc gv11b_blcg_gr[] = { | ||
203 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | ||
204 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
205 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
206 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | ||
207 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | ||
208 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | ||
209 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
210 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | ||
211 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | ||
212 | {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
213 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | ||
214 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
215 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | ||
216 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | ||
217 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | ||
218 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | ||
219 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | ||
220 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | ||
221 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | ||
222 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
223 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
224 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
225 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
226 | {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
227 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | ||
228 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | ||
229 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | ||
230 | {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, | ||
231 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
232 | {.addr = 0x00419c80, .prod = 0x00004045, .disable = 0x00000000}, | ||
233 | {.addr = 0x00419c88, .prod = 0x00004043, .disable = 0x00000000}, | ||
234 | {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, | ||
235 | {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, | ||
236 | {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, | ||
237 | {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, | ||
238 | {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, | ||
239 | {.addr = 0x00419a40, .prod = 0x00000242, .disable = 0x00000000}, | ||
240 | {.addr = 0x00419a48, .prod = 0x00000242, .disable = 0x00000000}, | ||
241 | {.addr = 0x00419a50, .prod = 0x00000242, .disable = 0x00000000}, | ||
242 | {.addr = 0x00419a58, .prod = 0x00000242, .disable = 0x00000000}, | ||
243 | {.addr = 0x00419a60, .prod = 0x00000202, .disable = 0x00000000}, | ||
244 | {.addr = 0x00419a68, .prod = 0x00000202, .disable = 0x00000000}, | ||
245 | {.addr = 0x00419a78, .prod = 0x00000242, .disable = 0x00000000}, | ||
246 | {.addr = 0x00419a80, .prod = 0x00000242, .disable = 0x00000000}, | ||
247 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | ||
248 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | ||
249 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
250 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | ||
251 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
252 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
253 | }; | ||
254 | |||
255 | /* blcg ltc */ | ||
256 | static const struct gating_desc gv11b_blcg_ltc[] = { | ||
257 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | ||
258 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | ||
259 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
260 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
261 | }; | ||
262 | |||
263 | /* blcg pwr_csb */ | ||
264 | static const struct gating_desc gv11b_blcg_pwr_csb[] = { | ||
265 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | ||
266 | }; | ||
267 | |||
268 | /* blcg pmu */ | ||
269 | static const struct gating_desc gv11b_blcg_pmu[] = { | ||
270 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | ||
271 | }; | ||
272 | |||
273 | /* blcg Xbar */ | ||
274 | static const struct gating_desc gv11b_blcg_xbar[] = { | ||
275 | {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, | ||
276 | {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, | ||
277 | {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, | ||
278 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | ||
279 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | ||
280 | }; | ||
281 | |||
282 | /* pg gr */ | ||
283 | static const struct gating_desc gv11b_pg_gr[] = { | ||
284 | }; | ||
285 | |||
286 | /* inline functions */ | ||
287 | void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, | ||
288 | bool prod) | ||
289 | { | ||
290 | u32 i; | ||
291 | u32 size = sizeof(gv11b_slcg_bus) / sizeof(struct gating_desc); | ||
292 | |||
293 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
294 | return; | ||
295 | |||
296 | for (i = 0; i < size; i++) { | ||
297 | if (prod) | ||
298 | gk20a_writel(g, gv11b_slcg_bus[i].addr, | ||
299 | gv11b_slcg_bus[i].prod); | ||
300 | else | ||
301 | gk20a_writel(g, gv11b_slcg_bus[i].addr, | ||
302 | gv11b_slcg_bus[i].disable); | ||
303 | } | ||
304 | } | ||
305 | |||
306 | void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
307 | bool prod) | ||
308 | { | ||
309 | u32 i; | ||
310 | u32 size = sizeof(gv11b_slcg_ce2) / sizeof(struct gating_desc); | ||
311 | |||
312 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
313 | return; | ||
314 | |||
315 | for (i = 0; i < size; i++) { | ||
316 | if (prod) | ||
317 | gk20a_writel(g, gv11b_slcg_ce2[i].addr, | ||
318 | gv11b_slcg_ce2[i].prod); | ||
319 | else | ||
320 | gk20a_writel(g, gv11b_slcg_ce2[i].addr, | ||
321 | gv11b_slcg_ce2[i].disable); | ||
322 | } | ||
323 | } | ||
324 | |||
325 | void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
326 | bool prod) | ||
327 | { | ||
328 | u32 i; | ||
329 | u32 size = sizeof(gv11b_slcg_chiplet) / sizeof(struct gating_desc); | ||
330 | |||
331 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
332 | return; | ||
333 | |||
334 | for (i = 0; i < size; i++) { | ||
335 | if (prod) | ||
336 | gk20a_writel(g, gv11b_slcg_chiplet[i].addr, | ||
337 | gv11b_slcg_chiplet[i].prod); | ||
338 | else | ||
339 | gk20a_writel(g, gv11b_slcg_chiplet[i].addr, | ||
340 | gv11b_slcg_chiplet[i].disable); | ||
341 | } | ||
342 | } | ||
343 | |||
344 | void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
345 | bool prod) | ||
346 | { | ||
347 | } | ||
348 | |||
349 | void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, | ||
350 | bool prod) | ||
351 | { | ||
352 | u32 i; | ||
353 | u32 size = sizeof(gv11b_slcg_fb) / sizeof(struct gating_desc); | ||
354 | |||
355 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
356 | return; | ||
357 | |||
358 | for (i = 0; i < size; i++) { | ||
359 | if (prod) | ||
360 | gk20a_writel(g, gv11b_slcg_fb[i].addr, | ||
361 | gv11b_slcg_fb[i].prod); | ||
362 | else | ||
363 | gk20a_writel(g, gv11b_slcg_fb[i].addr, | ||
364 | gv11b_slcg_fb[i].disable); | ||
365 | } | ||
366 | } | ||
367 | |||
368 | void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
369 | bool prod) | ||
370 | { | ||
371 | u32 i; | ||
372 | u32 size = sizeof(gv11b_slcg_fifo) / sizeof(struct gating_desc); | ||
373 | |||
374 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
375 | return; | ||
376 | |||
377 | for (i = 0; i < size; i++) { | ||
378 | if (prod) | ||
379 | gk20a_writel(g, gv11b_slcg_fifo[i].addr, | ||
380 | gv11b_slcg_fifo[i].prod); | ||
381 | else | ||
382 | gk20a_writel(g, gv11b_slcg_fifo[i].addr, | ||
383 | gv11b_slcg_fifo[i].disable); | ||
384 | } | ||
385 | } | ||
386 | |||
387 | void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
388 | bool prod) | ||
389 | { | ||
390 | u32 i; | ||
391 | u32 size = sizeof(gv11b_slcg_gr) / sizeof(struct gating_desc); | ||
392 | |||
393 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
394 | return; | ||
395 | |||
396 | for (i = 0; i < size; i++) { | ||
397 | if (prod) | ||
398 | gk20a_writel(g, gv11b_slcg_gr[i].addr, | ||
399 | gv11b_slcg_gr[i].prod); | ||
400 | else | ||
401 | gk20a_writel(g, gv11b_slcg_gr[i].addr, | ||
402 | gv11b_slcg_gr[i].disable); | ||
403 | } | ||
404 | } | ||
405 | |||
406 | void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
407 | bool prod) | ||
408 | { | ||
409 | u32 i; | ||
410 | u32 size = sizeof(gv11b_slcg_ltc) / sizeof(struct gating_desc); | ||
411 | |||
412 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
413 | return; | ||
414 | |||
415 | for (i = 0; i < size; i++) { | ||
416 | if (prod) | ||
417 | gk20a_writel(g, gv11b_slcg_ltc[i].addr, | ||
418 | gv11b_slcg_ltc[i].prod); | ||
419 | else | ||
420 | gk20a_writel(g, gv11b_slcg_ltc[i].addr, | ||
421 | gv11b_slcg_ltc[i].disable); | ||
422 | } | ||
423 | } | ||
424 | |||
425 | void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
426 | bool prod) | ||
427 | { | ||
428 | u32 i; | ||
429 | u32 size = sizeof(gv11b_slcg_perf) / sizeof(struct gating_desc); | ||
430 | |||
431 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
432 | return; | ||
433 | |||
434 | for (i = 0; i < size; i++) { | ||
435 | if (prod) | ||
436 | gk20a_writel(g, gv11b_slcg_perf[i].addr, | ||
437 | gv11b_slcg_perf[i].prod); | ||
438 | else | ||
439 | gk20a_writel(g, gv11b_slcg_perf[i].addr, | ||
440 | gv11b_slcg_perf[i].disable); | ||
441 | } | ||
442 | } | ||
443 | |||
444 | void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, | ||
445 | bool prod) | ||
446 | { | ||
447 | u32 i; | ||
448 | u32 size = sizeof(gv11b_slcg_priring) / sizeof(struct gating_desc); | ||
449 | |||
450 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
451 | return; | ||
452 | |||
453 | for (i = 0; i < size; i++) { | ||
454 | if (prod) | ||
455 | gk20a_writel(g, gv11b_slcg_priring[i].addr, | ||
456 | gv11b_slcg_priring[i].prod); | ||
457 | else | ||
458 | gk20a_writel(g, gv11b_slcg_priring[i].addr, | ||
459 | gv11b_slcg_priring[i].disable); | ||
460 | } | ||
461 | } | ||
462 | |||
463 | void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
464 | bool prod) | ||
465 | { | ||
466 | u32 i; | ||
467 | u32 size = sizeof(gv11b_slcg_pwr_csb) / sizeof(struct gating_desc); | ||
468 | |||
469 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
470 | return; | ||
471 | |||
472 | for (i = 0; i < size; i++) { | ||
473 | if (prod) | ||
474 | gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, | ||
475 | gv11b_slcg_pwr_csb[i].prod); | ||
476 | else | ||
477 | gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, | ||
478 | gv11b_slcg_pwr_csb[i].disable); | ||
479 | } | ||
480 | } | ||
481 | |||
482 | void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
483 | bool prod) | ||
484 | { | ||
485 | u32 i; | ||
486 | u32 size = sizeof(gv11b_slcg_pmu) / sizeof(struct gating_desc); | ||
487 | |||
488 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
489 | return; | ||
490 | |||
491 | for (i = 0; i < size; i++) { | ||
492 | if (prod) | ||
493 | gk20a_writel(g, gv11b_slcg_pmu[i].addr, | ||
494 | gv11b_slcg_pmu[i].prod); | ||
495 | else | ||
496 | gk20a_writel(g, gv11b_slcg_pmu[i].addr, | ||
497 | gv11b_slcg_pmu[i].disable); | ||
498 | } | ||
499 | } | ||
500 | |||
501 | void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
502 | bool prod) | ||
503 | { | ||
504 | u32 i; | ||
505 | u32 size = sizeof(gv11b_slcg_therm) / sizeof(struct gating_desc); | ||
506 | |||
507 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
508 | return; | ||
509 | |||
510 | for (i = 0; i < size; i++) { | ||
511 | if (prod) | ||
512 | gk20a_writel(g, gv11b_slcg_therm[i].addr, | ||
513 | gv11b_slcg_therm[i].prod); | ||
514 | else | ||
515 | gk20a_writel(g, gv11b_slcg_therm[i].addr, | ||
516 | gv11b_slcg_therm[i].disable); | ||
517 | } | ||
518 | } | ||
519 | |||
520 | void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
521 | bool prod) | ||
522 | { | ||
523 | u32 i; | ||
524 | u32 size = sizeof(gv11b_slcg_xbar) / sizeof(struct gating_desc); | ||
525 | |||
526 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
527 | return; | ||
528 | |||
529 | for (i = 0; i < size; i++) { | ||
530 | if (prod) | ||
531 | gk20a_writel(g, gv11b_slcg_xbar[i].addr, | ||
532 | gv11b_slcg_xbar[i].prod); | ||
533 | else | ||
534 | gk20a_writel(g, gv11b_slcg_xbar[i].addr, | ||
535 | gv11b_slcg_xbar[i].disable); | ||
536 | } | ||
537 | } | ||
538 | |||
539 | void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, | ||
540 | bool prod) | ||
541 | { | ||
542 | u32 i; | ||
543 | u32 size = sizeof(gv11b_blcg_bus) / sizeof(struct gating_desc); | ||
544 | |||
545 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
546 | return; | ||
547 | |||
548 | for (i = 0; i < size; i++) { | ||
549 | if (prod) | ||
550 | gk20a_writel(g, gv11b_blcg_bus[i].addr, | ||
551 | gv11b_blcg_bus[i].prod); | ||
552 | else | ||
553 | gk20a_writel(g, gv11b_blcg_bus[i].addr, | ||
554 | gv11b_blcg_bus[i].disable); | ||
555 | } | ||
556 | } | ||
557 | |||
558 | void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, | ||
559 | bool prod) | ||
560 | { | ||
561 | u32 i; | ||
562 | u32 size = sizeof(gv11b_blcg_ce) / sizeof(struct gating_desc); | ||
563 | |||
564 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
565 | return; | ||
566 | |||
567 | for (i = 0; i < size; i++) { | ||
568 | if (prod) | ||
569 | gk20a_writel(g, gv11b_blcg_ce[i].addr, | ||
570 | gv11b_blcg_ce[i].prod); | ||
571 | else | ||
572 | gk20a_writel(g, gv11b_blcg_ce[i].addr, | ||
573 | gv11b_blcg_ce[i].disable); | ||
574 | } | ||
575 | } | ||
576 | |||
577 | void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
578 | bool prod) | ||
579 | { | ||
580 | u32 i; | ||
581 | u32 size = sizeof(gv11b_blcg_ctxsw_prog) / sizeof(struct gating_desc); | ||
582 | |||
583 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
584 | return; | ||
585 | |||
586 | for (i = 0; i < size; i++) { | ||
587 | if (prod) | ||
588 | gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, | ||
589 | gv11b_blcg_ctxsw_prog[i].prod); | ||
590 | else | ||
591 | gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, | ||
592 | gv11b_blcg_ctxsw_prog[i].disable); | ||
593 | } | ||
594 | } | ||
595 | |||
596 | void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, | ||
597 | bool prod) | ||
598 | { | ||
599 | u32 i; | ||
600 | u32 size = sizeof(gv11b_blcg_fb) / sizeof(struct gating_desc); | ||
601 | |||
602 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
603 | return; | ||
604 | |||
605 | for (i = 0; i < size; i++) { | ||
606 | if (prod) | ||
607 | gk20a_writel(g, gv11b_blcg_fb[i].addr, | ||
608 | gv11b_blcg_fb[i].prod); | ||
609 | else | ||
610 | gk20a_writel(g, gv11b_blcg_fb[i].addr, | ||
611 | gv11b_blcg_fb[i].disable); | ||
612 | } | ||
613 | } | ||
614 | |||
615 | void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
616 | bool prod) | ||
617 | { | ||
618 | u32 i; | ||
619 | u32 size = sizeof(gv11b_blcg_fifo) / sizeof(struct gating_desc); | ||
620 | |||
621 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
622 | return; | ||
623 | |||
624 | for (i = 0; i < size; i++) { | ||
625 | if (prod) | ||
626 | gk20a_writel(g, gv11b_blcg_fifo[i].addr, | ||
627 | gv11b_blcg_fifo[i].prod); | ||
628 | else | ||
629 | gk20a_writel(g, gv11b_blcg_fifo[i].addr, | ||
630 | gv11b_blcg_fifo[i].disable); | ||
631 | } | ||
632 | } | ||
633 | |||
634 | void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
635 | bool prod) | ||
636 | { | ||
637 | u32 i; | ||
638 | u32 size = sizeof(gv11b_blcg_gr) / sizeof(struct gating_desc); | ||
639 | |||
640 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
641 | return; | ||
642 | |||
643 | for (i = 0; i < size; i++) { | ||
644 | if (prod) | ||
645 | gk20a_writel(g, gv11b_blcg_gr[i].addr, | ||
646 | gv11b_blcg_gr[i].prod); | ||
647 | else | ||
648 | gk20a_writel(g, gv11b_blcg_gr[i].addr, | ||
649 | gv11b_blcg_gr[i].disable); | ||
650 | } | ||
651 | } | ||
652 | |||
653 | void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
654 | bool prod) | ||
655 | { | ||
656 | u32 i; | ||
657 | u32 size = sizeof(gv11b_blcg_ltc) / sizeof(struct gating_desc); | ||
658 | |||
659 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
660 | return; | ||
661 | |||
662 | for (i = 0; i < size; i++) { | ||
663 | if (prod) | ||
664 | gk20a_writel(g, gv11b_blcg_ltc[i].addr, | ||
665 | gv11b_blcg_ltc[i].prod); | ||
666 | else | ||
667 | gk20a_writel(g, gv11b_blcg_ltc[i].addr, | ||
668 | gv11b_blcg_ltc[i].disable); | ||
669 | } | ||
670 | } | ||
671 | |||
672 | void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
673 | bool prod) | ||
674 | { | ||
675 | u32 i; | ||
676 | u32 size = sizeof(gv11b_blcg_pwr_csb) / sizeof(struct gating_desc); | ||
677 | |||
678 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
679 | return; | ||
680 | |||
681 | for (i = 0; i < size; i++) { | ||
682 | if (prod) | ||
683 | gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, | ||
684 | gv11b_blcg_pwr_csb[i].prod); | ||
685 | else | ||
686 | gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, | ||
687 | gv11b_blcg_pwr_csb[i].disable); | ||
688 | } | ||
689 | } | ||
690 | |||
691 | void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
692 | bool prod) | ||
693 | { | ||
694 | u32 i; | ||
695 | u32 size = sizeof(gv11b_blcg_pmu) / sizeof(struct gating_desc); | ||
696 | |||
697 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
698 | return; | ||
699 | |||
700 | for (i = 0; i < size; i++) { | ||
701 | if (prod) | ||
702 | gk20a_writel(g, gv11b_blcg_pmu[i].addr, | ||
703 | gv11b_blcg_pmu[i].prod); | ||
704 | else | ||
705 | gk20a_writel(g, gv11b_blcg_pmu[i].addr, | ||
706 | gv11b_blcg_pmu[i].disable); | ||
707 | } | ||
708 | } | ||
709 | |||
710 | void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
711 | bool prod) | ||
712 | { | ||
713 | u32 i; | ||
714 | u32 size = sizeof(gv11b_blcg_xbar) / sizeof(struct gating_desc); | ||
715 | |||
716 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
717 | return; | ||
718 | |||
719 | for (i = 0; i < size; i++) { | ||
720 | if (prod) | ||
721 | gk20a_writel(g, gv11b_blcg_xbar[i].addr, | ||
722 | gv11b_blcg_xbar[i].prod); | ||
723 | else | ||
724 | gk20a_writel(g, gv11b_blcg_xbar[i].addr, | ||
725 | gv11b_blcg_xbar[i].disable); | ||
726 | } | ||
727 | } | ||
728 | |||
729 | void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, | ||
730 | bool prod) | ||
731 | { | ||
732 | u32 i; | ||
733 | u32 size = sizeof(gv11b_pg_gr) / sizeof(struct gating_desc); | ||
734 | |||
735 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
736 | return; | ||
737 | |||
738 | for (i = 0; i < size; i++) { | ||
739 | if (prod) | ||
740 | gk20a_writel(g, gv11b_pg_gr[i].addr, | ||
741 | gv11b_pg_gr[i].prod); | ||
742 | else | ||
743 | gk20a_writel(g, gv11b_pg_gr[i].addr, | ||
744 | gv11b_pg_gr[i].disable); | ||
745 | } | ||
746 | } | ||
747 | |||
748 | #endif /* __gv11b_gating_reglist_h__ */ | ||