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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.h215
1 files changed, 215 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
new file mode 100644
index 00000000..b6ba231e
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -0,0 +1,215 @@
1/*
2 * GV11B GPU GR
3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _NVGPU_GR_GV11B_H_
26#define _NVGPU_GR_GV11B_H_
27
28#define EGPC_PRI_BASE 0x580000
29#define EGPC_PRI_SHARED_BASE 0x480000
30
31#define PRI_BROADCAST_FLAGS_SMPC BIT(17)
32
33#define GV11B_ZBC_TYPE_STENCIL T19X_ZBC
34#define ZBC_STENCIL_CLEAR_FMT_INVAILD 0
35#define ZBC_STENCIL_CLEAR_FMT_U8 1
36
37struct zbc_s_table {
38 u32 stencil;
39 u32 format;
40 u32 ref_cnt;
41};
42
43struct gk20a;
44struct zbc_entry;
45struct zbc_query_params;
46struct channel_ctx_gk20a;
47struct nvgpu_warpstate;
48struct nvgpu_gr_sm_error_state;
49
50enum {
51 VOLTA_CHANNEL_GPFIFO_A = 0xC36F,
52 VOLTA_A = 0xC397,
53 VOLTA_COMPUTE_A = 0xC3C0,
54 VOLTA_DMA_COPY_A = 0xC3B5,
55};
56
57#define NVC397_SET_SHADER_EXCEPTIONS 0x1528
58#define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280
59#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
60#define NVC397_SET_GO_IDLE_TIMEOUT 0x022c
61#define NVC397_SET_TEX_IN_DBG 0x10bc
62#define NVC397_SET_SKEDCHECK 0x10c0
63#define NVC397_SET_BES_CROP_DEBUG3 0x10c4
64
65#define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1
66#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2
67#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST 0x4
68
69#define NVC397_SET_SKEDCHECK_18_MASK 0x3
70#define NVC397_SET_SKEDCHECK_18_DEFAULT 0x0
71#define NVC397_SET_SKEDCHECK_18_DISABLE 0x1
72#define NVC397_SET_SKEDCHECK_18_ENABLE 0x2
73
74#define NVC3C0_SET_SKEDCHECK 0x23c
75
76#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0
77
78int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size,
79 struct nvgpu_mem *mem);
80/*zcull*/
81void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries,
82 u32 *zcull_map_tiles);
83void gr_gv11b_create_sysfs(struct gk20a *g);
84
85bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num);
86bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num);
87bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num);
88void gr_gv11b_enable_hww_exceptions(struct gk20a *g);
89void gr_gv11b_enable_exceptions(struct gk20a *g);
90int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g,
91 u32 gpc, u32 tpc,
92 bool *post_event, struct channel_gk20a *fault_ch,
93 u32 *hww_global_esr);
94int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc,
95 bool *post_event, struct channel_gk20a *fault_ch,
96 u32 *hww_global_esr);
97int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc,
98 u32 gpc_exception);
99int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc,
100 u32 gpc_exception);
101void gr_gv11b_enable_gpc_exceptions(struct gk20a *g);
102int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
103 bool *post_event);
104int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr,
105 struct zbc_query_params *query_params);
106bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr,
107 struct zbc_entry *zbc_val, int *ret_val);
108int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr,
109 struct zbc_entry *stencil_val, u32 index);
110int gr_gv11b_load_stencil_default_tbl(struct gk20a *g,
111 struct gr_gk20a *gr);
112int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr);
113u32 gr_gv11b_pagepool_default_size(struct gk20a *g);
114int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g);
115int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
116 u32 class_num, u32 offset, u32 data);
117void gr_gv11b_bundle_cb_defaults(struct gk20a *g);
118void gr_gv11b_cb_size_default(struct gk20a *g);
119void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
120void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data);
121int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
122 struct gk20a_debug_output *o);
123int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms,
124 u32 expect_delay);
125void gr_gv11b_commit_global_attrib_cb(struct gk20a *g,
126 struct channel_ctx_gk20a *ch_ctx,
127 u64 addr, bool patch);
128void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
129void gr_gv11b_get_access_map(struct gk20a *g,
130 u32 **whitelist, int *num_entries);
131int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
132 u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
133 bool sm_debugger_attached, struct channel_gk20a *fault_ch,
134 bool *early_exit, bool *ignore_debugger);
135int gr_gv11b_handle_fecs_error(struct gk20a *g,
136 struct channel_gk20a *__ch,
137 struct gr_gk20a_isr_data *isr_data);
138int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr);
139int gr_gv11b_init_sw_veid_bundle(struct gk20a *g);
140void gr_gv11b_detect_sm_arch(struct gk20a *g);
141void gr_gv11b_program_sm_id_numbering(struct gk20a *g,
142 u32 gpc, u32 tpc, u32 smid);
143int gr_gv11b_load_smid_config(struct gk20a *g);
144int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va);
145int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c);
146void gr_gv11b_write_zcull_ptr(struct gk20a *g,
147 struct nvgpu_mem *mem, u64 gpu_va);
148void gr_gv11b_write_pm_ptr(struct gk20a *g,
149 struct nvgpu_mem *mem, u64 gpu_va);
150void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine);
151void gr_gv11b_load_tpc_mask(struct gk20a *g);
152void gr_gv11b_set_preemption_buffer_va(struct gk20a *g,
153 struct nvgpu_mem *mem, u64 gpu_va);
154int gr_gv11b_init_fs_state(struct gk20a *g);
155void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
156 u32 *esr_sm_sel);
157int gv11b_gr_sm_trigger_suspend(struct gk20a *g);
158void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state);
159int gv11b_gr_update_sm_error_state(struct gk20a *g,
160 struct channel_gk20a *ch, u32 sm_id,
161 struct nvgpu_gr_sm_error_state *sm_error_state);
162int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
163 struct channel_gk20a *ch, u64 sms, bool enable);
164int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc);
165void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g);
166bool gv11b_gr_sm_debugger_attached(struct gk20a *g);
167void gv11b_gr_suspend_single_sm(struct gk20a *g,
168 u32 gpc, u32 tpc, u32 sm,
169 u32 global_esr_mask, bool check_errors);
170void gv11b_gr_suspend_all_sms(struct gk20a *g,
171 u32 global_esr_mask, bool check_errors);
172void gv11b_gr_resume_single_sm(struct gk20a *g,
173 u32 gpc, u32 tpc, u32 sm);
174void gv11b_gr_resume_all_sms(struct gk20a *g);
175int gv11b_gr_resume_from_pause(struct gk20a *g);
176u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g,
177 u32 gpc, u32 tpc, u32 sm);
178u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g,
179 u32 gpc, u32 tpc, u32 sm);
180u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g);
181int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g,
182 u32 gpc, u32 tpc, u32 sm,
183 u32 global_esr_mask, bool check_errors);
184int gv11b_gr_lock_down_sm(struct gk20a *g,
185 u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask,
186 bool check_errors);
187void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
188 u32 global_esr);
189int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g,
190 u32 gpc, u32 tpc, bool *post_event);
191void gv11b_gr_init_ovr_sm_dsm_perf(void);
192void gv11b_gr_init_sm_dsm_reg_info(void);
193void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g,
194 u32 *num_sm_dsm_perf_regs,
195 u32 **sm_dsm_perf_regs,
196 u32 *perf_register_stride);
197void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
198 u32 *num_sm_dsm_perf_ctrl_regs,
199 u32 **sm_dsm_perf_ctrl_regs,
200 u32 *ctrl_register_stride);
201void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs,
202 u32 **ovr_perf_regs);
203void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset);
204bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr);
205bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr);
206void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr,
207 u32 *egpc_num, u32 *etpc_num);
208int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type,
209 u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags);
210void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
211 u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t);
212u32 gv11b_gr_get_egpc_base(struct gk20a *g);
213void gr_gv11b_init_gpc_mmu(struct gk20a *g);
214
215#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 01:04:14 -0400