diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 116 |
1 files changed, 115 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 6ceaa47a..d3fe5f65 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -4488,11 +4488,125 @@ static int gr_gv11b_ecc_scrub_sm_icahe(struct gk20a *g) | |||
4488 | scrub_mask, scrub_done); | 4488 | scrub_mask, scrub_done); |
4489 | } | 4489 | } |
4490 | 4490 | ||
4491 | static void gr_gv11b_detect_ecc_enabled_units(struct gk20a *g) | ||
4492 | { | ||
4493 | bool opt_ecc_en = g->ops.fuse.is_opt_ecc_enable(g); | ||
4494 | bool opt_feature_fuses_override_disable = | ||
4495 | g->ops.fuse.is_opt_feature_override_disable(g); | ||
4496 | u32 fecs_feature_override_ecc = | ||
4497 | gk20a_readl(g, | ||
4498 | gr_fecs_feature_override_ecc_r()); | ||
4499 | |||
4500 | if (opt_feature_fuses_override_disable) { | ||
4501 | if (opt_ecc_en) { | ||
4502 | __nvgpu_set_enabled(g, | ||
4503 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
4504 | __nvgpu_set_enabled(g, | ||
4505 | NVGPU_ECC_ENABLED_SM_L1_DATA, true); | ||
4506 | __nvgpu_set_enabled(g, | ||
4507 | NVGPU_ECC_ENABLED_SM_L1_TAG, true); | ||
4508 | __nvgpu_set_enabled(g, | ||
4509 | NVGPU_ECC_ENABLED_SM_ICACHE, true); | ||
4510 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true); | ||
4511 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true); | ||
4512 | } | ||
4513 | } else { | ||
4514 | /* SM LRF */ | ||
4515 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( | ||
4516 | fecs_feature_override_ecc) == 1U) { | ||
4517 | if (gr_fecs_feature_override_ecc_sm_lrf_v( | ||
4518 | fecs_feature_override_ecc) == 1U) { | ||
4519 | __nvgpu_set_enabled(g, | ||
4520 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
4521 | } | ||
4522 | } else { | ||
4523 | if (opt_ecc_en) { | ||
4524 | __nvgpu_set_enabled(g, | ||
4525 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
4526 | } | ||
4527 | } | ||
4528 | /* SM L1 DATA*/ | ||
4529 | if (gr_fecs_feature_override_ecc_sm_l1_data_override_v( | ||
4530 | fecs_feature_override_ecc) == 1U) { | ||
4531 | if (gr_fecs_feature_override_ecc_sm_l1_data_v( | ||
4532 | fecs_feature_override_ecc) == 1U) { | ||
4533 | __nvgpu_set_enabled(g, | ||
4534 | NVGPU_ECC_ENABLED_SM_L1_DATA, true); | ||
4535 | } | ||
4536 | } else { | ||
4537 | if (opt_ecc_en) { | ||
4538 | __nvgpu_set_enabled(g, | ||
4539 | NVGPU_ECC_ENABLED_SM_L1_DATA, true); | ||
4540 | } | ||
4541 | } | ||
4542 | /* SM L1 TAG*/ | ||
4543 | if (gr_fecs_feature_override_ecc_sm_l1_tag_override_v( | ||
4544 | fecs_feature_override_ecc) == 1U) { | ||
4545 | if (gr_fecs_feature_override_ecc_sm_l1_tag_v( | ||
4546 | fecs_feature_override_ecc) == 1U) { | ||
4547 | __nvgpu_set_enabled(g, | ||
4548 | NVGPU_ECC_ENABLED_SM_L1_TAG, true); | ||
4549 | } | ||
4550 | } else { | ||
4551 | if (opt_ecc_en) { | ||
4552 | __nvgpu_set_enabled(g, | ||
4553 | NVGPU_ECC_ENABLED_SM_L1_TAG, true); | ||
4554 | } | ||
4555 | } | ||
4556 | /* SM ICACHE*/ | ||
4557 | if ((gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v( | ||
4558 | fecs_feature_override_ecc) == 1U) && | ||
4559 | (gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v( | ||
4560 | fecs_feature_override_ecc) == 1U)) { | ||
4561 | if ((gr_fecs_feature_override_ecc_1_sm_l0_icache_v( | ||
4562 | fecs_feature_override_ecc) == 1U) && | ||
4563 | (gr_fecs_feature_override_ecc_1_sm_l1_icache_v( | ||
4564 | fecs_feature_override_ecc) == 1U)) { | ||
4565 | __nvgpu_set_enabled(g, | ||
4566 | NVGPU_ECC_ENABLED_SM_ICACHE, true); | ||
4567 | } | ||
4568 | } else { | ||
4569 | if (opt_ecc_en) { | ||
4570 | __nvgpu_set_enabled(g, | ||
4571 | NVGPU_ECC_ENABLED_SM_ICACHE, true); | ||
4572 | } | ||
4573 | } | ||
4574 | /* LTC */ | ||
4575 | if (gr_fecs_feature_override_ecc_ltc_override_v( | ||
4576 | fecs_feature_override_ecc) == 1U) { | ||
4577 | if (gr_fecs_feature_override_ecc_ltc_v( | ||
4578 | fecs_feature_override_ecc) == 1U) { | ||
4579 | __nvgpu_set_enabled(g, | ||
4580 | NVGPU_ECC_ENABLED_LTC, true); | ||
4581 | } | ||
4582 | } else { | ||
4583 | if (opt_ecc_en) { | ||
4584 | __nvgpu_set_enabled(g, | ||
4585 | NVGPU_ECC_ENABLED_LTC, true); | ||
4586 | } | ||
4587 | } | ||
4588 | /* SM CBU */ | ||
4589 | if (gr_fecs_feature_override_ecc_sm_cbu_override_v( | ||
4590 | fecs_feature_override_ecc) == 1U) { | ||
4591 | if (gr_fecs_feature_override_ecc_sm_cbu_v( | ||
4592 | fecs_feature_override_ecc) == 1U) { | ||
4593 | __nvgpu_set_enabled(g, | ||
4594 | NVGPU_ECC_ENABLED_SM_CBU, true); | ||
4595 | } | ||
4596 | } else { | ||
4597 | if (opt_ecc_en) { | ||
4598 | __nvgpu_set_enabled(g, | ||
4599 | NVGPU_ECC_ENABLED_SM_CBU, true); | ||
4600 | } | ||
4601 | } | ||
4602 | } | ||
4603 | } | ||
4604 | |||
4491 | void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g) | 4605 | void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g) |
4492 | { | 4606 | { |
4493 | nvgpu_log_fn(g, "ecc srub start "); | 4607 | nvgpu_log_fn(g, "ecc srub start "); |
4494 | 4608 | ||
4495 | gv11b_detect_ecc_enabled_units(g); | 4609 | gr_gv11b_detect_ecc_enabled_units(g); |
4496 | 4610 | ||
4497 | if (gr_gv11b_ecc_scrub_sm_lrf(g)) | 4611 | if (gr_gv11b_ecc_scrub_sm_lrf(g)) |
4498 | nvgpu_warn(g, "ECC SCRUB SM LRF Failed"); | 4612 | nvgpu_warn(g, "ECC SCRUB SM LRF Failed"); |