diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index c925e5b6..9e36071f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -2182,9 +2182,9 @@ static bool gr_gv11b_check_warp_esr_error(struct gk20a *g, u32 warp_esr_error) | |||
2182 | 2182 | ||
2183 | struct warp_esr_error_table_s warp_esr_error_table[] = { | 2183 | struct warp_esr_error_table_s warp_esr_error_table[] = { |
2184 | { gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f(), | 2184 | { gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f(), |
2185 | "STACK ERROR"}, | 2185 | "STACK ERROR"}, |
2186 | { gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(), | 2186 | { gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(), |
2187 | "API STACK ERROR"}, | 2187 | "API STACK ERROR"}, |
2188 | { gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f(), | 2188 | { gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f(), |
2189 | "PC WRAP ERROR"}, | 2189 | "PC WRAP ERROR"}, |
2190 | { gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(), | 2190 | { gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(), |
@@ -2221,7 +2221,7 @@ static bool gr_gv11b_check_warp_esr_error(struct gk20a *g, u32 warp_esr_error) | |||
2221 | if (warp_esr_error_table[index].error_value == warp_esr_error) { | 2221 | if (warp_esr_error_table[index].error_value == warp_esr_error) { |
2222 | esr_err = warp_esr_error_table[index].error_value; | 2222 | esr_err = warp_esr_error_table[index].error_value; |
2223 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | 2223 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, |
2224 | "ESR %s(0x%x)", | 2224 | "WARP_ESR %s(0x%x)", |
2225 | warp_esr_error_table[index].error_name, | 2225 | warp_esr_error_table[index].error_name, |
2226 | esr_err); | 2226 | esr_err); |
2227 | break; | 2227 | break; |
@@ -2250,6 +2250,21 @@ static int gr_gv11b_handle_all_warp_esr_errors(struct gk20a *g, | |||
2250 | return 0; | 2250 | return 0; |
2251 | } | 2251 | } |
2252 | 2252 | ||
2253 | /* | ||
2254 | * Check SET_EXCEPTION_TYPE_MASK is being set. | ||
2255 | * If set, skip the recovery and trigger CILP | ||
2256 | * If not set, trigger the recovery. | ||
2257 | */ | ||
2258 | if ((g->gr.sm_exception_mask_type & | ||
2259 | NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL) == | ||
2260 | NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL) { | ||
2261 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
2262 | "SM Exception Type Mask set %d," | ||
2263 | "skip recovery", | ||
2264 | g->gr.sm_exception_mask_type); | ||
2265 | return 0; | ||
2266 | } | ||
2267 | |||
2253 | if (fault_ch) { | 2268 | if (fault_ch) { |
2254 | tsg = &g->fifo.tsg[fault_ch->tsgid]; | 2269 | tsg = &g->fifo.tsg[fault_ch->tsgid]; |
2255 | 2270 | ||
@@ -2294,7 +2309,6 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
2294 | u32 warp_esr_error = gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(warp_esr); | 2309 | u32 warp_esr_error = gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(warp_esr); |
2295 | struct tsg_gk20a *tsg; | 2310 | struct tsg_gk20a *tsg; |
2296 | 2311 | ||
2297 | |||
2298 | *early_exit = false; | 2312 | *early_exit = false; |
2299 | *ignore_debugger = false; | 2313 | *ignore_debugger = false; |
2300 | 2314 | ||