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path: root/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c36
1 files changed, 0 insertions, 36 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 058a21e5..c2cf909a 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -58,7 +58,6 @@
58#include <nvgpu/hw/gv11b/hw_mc_gv11b.h> 58#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
59#include <nvgpu/hw/gv11b/hw_ram_gv11b.h> 59#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
60#include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> 60#include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
61#include <nvgpu/hw/gv11b/hw_therm_gv11b.h>
62#include <nvgpu/hw/gv11b/hw_perf_gv11b.h> 61#include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
63#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h> 62#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
64 63
@@ -2915,41 +2914,6 @@ void gr_gv11b_write_pm_ptr(struct gk20a *g,
2915 ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); 2914 ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi);
2916} 2915}
2917 2916
2918void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
2919{
2920 u32 gate_ctrl;
2921
2922 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG))
2923 return;
2924
2925 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine));
2926
2927 switch (mode) {
2928 case ELCG_RUN:
2929 gate_ctrl = set_field(gate_ctrl,
2930 therm_gate_ctrl_eng_clk_m(),
2931 therm_gate_ctrl_eng_clk_run_f());
2932 gate_ctrl = set_field(gate_ctrl,
2933 therm_gate_ctrl_idle_holdoff_m(),
2934 therm_gate_ctrl_idle_holdoff_on_f());
2935 break;
2936 case ELCG_STOP:
2937 gate_ctrl = set_field(gate_ctrl,
2938 therm_gate_ctrl_eng_clk_m(),
2939 therm_gate_ctrl_eng_clk_stop_f());
2940 break;
2941 case ELCG_AUTO:
2942 gate_ctrl = set_field(gate_ctrl,
2943 therm_gate_ctrl_eng_clk_m(),
2944 therm_gate_ctrl_eng_clk_auto_f());
2945 break;
2946 default:
2947 nvgpu_err(g, "invalid elcg mode %d", mode);
2948 }
2949
2950 gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
2951}
2952
2953void gr_gv11b_load_tpc_mask(struct gk20a *g) 2917void gr_gv11b_load_tpc_mask(struct gk20a *g)
2954{ 2918{
2955 u32 pes_tpc_mask = 0, fuse_tpc_mask; 2919 u32 pes_tpc_mask = 0, fuse_tpc_mask;