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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
index 032342b2..8a2b32f8 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
@@ -17,6 +17,7 @@
17#define FIFO_GV11B_H 17#define FIFO_GV11B_H
18 18
19#define FIFO_INVAL_PBDMA_ID ((u32)~0) 19#define FIFO_INVAL_PBDMA_ID ((u32)~0)
20#define FIFO_INVAL_VEID ((u32)~0)
20 21
21/* engine context-switch request occurred while the engine was in reset */ 22/* engine context-switch request occurred while the engine was in reset */
22#define SCHED_ERROR_CODE_ENGINE_RESET 0x00000005 23#define SCHED_ERROR_CODE_ENGINE_RESET 0x00000005
@@ -43,4 +44,6 @@ void gv11b_init_fifo(struct gpu_ops *gops);
43void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, 44void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g,
44 struct channel_gk20a *refch, 45 struct channel_gk20a *refch,
45 u32 faulted_pbdma, u32 faulted_engine); 46 u32 faulted_pbdma, u32 faulted_engine);
47void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g,
48 u32 mmu_fault_id, u32 *active_engine_id, u32 *veid, u32 *pbdma_id);
46#endif 49#endif