diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 33 |
1 files changed, 18 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b0b752af..11ccdd48 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -22,6 +22,7 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <nvgpu/bug.h> | ||
25 | #include <nvgpu/semaphore.h> | 26 | #include <nvgpu/semaphore.h> |
26 | #include <nvgpu/timers.h> | 27 | #include <nvgpu/timers.h> |
27 | #include <nvgpu/log.h> | 28 | #include <nvgpu/log.h> |
@@ -803,17 +804,22 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, | |||
803 | int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid) | 804 | int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid) |
804 | { | 805 | { |
805 | struct fifo_gk20a *f = &g->fifo; | 806 | struct fifo_gk20a *f = &g->fifo; |
806 | u32 tsgid; | 807 | struct tsg_gk20a *tsg = NULL; |
807 | 808 | ||
808 | if (chid == FIFO_INVAL_CHANNEL_ID) { | 809 | if (chid == FIFO_INVAL_CHANNEL_ID) { |
809 | return 0; | 810 | return 0; |
810 | } | 811 | } |
811 | 812 | ||
812 | tsgid = f->channel[chid].tsgid; | 813 | tsg = tsg_gk20a_from_ch(&f->channel[chid]); |
813 | nvgpu_log_info(g, "chid:%d tsgid:%d", chid, tsgid); | 814 | |
815 | if (tsg == NULL) { | ||
816 | return 0; | ||
817 | } | ||
818 | |||
819 | nvgpu_log_info(g, "chid:%d tsgid:%d", chid, tsg->tsgid); | ||
814 | 820 | ||
815 | /* Preempt tsg. Channel preempt is NOOP */ | 821 | /* Preempt tsg. Channel preempt is NOOP */ |
816 | return g->ops.fifo.preempt_tsg(g, tsgid); | 822 | return g->ops.fifo.preempt_tsg(g, tsg); |
817 | } | 823 | } |
818 | 824 | ||
819 | /* TSG enable sequence applicable for Volta and onwards */ | 825 | /* TSG enable sequence applicable for Volta and onwards */ |
@@ -837,7 +843,7 @@ int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg) | |||
837 | return 0; | 843 | return 0; |
838 | } | 844 | } |
839 | 845 | ||
840 | int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) | 846 | int gv11b_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg) |
841 | { | 847 | { |
842 | struct fifo_gk20a *f = &g->fifo; | 848 | struct fifo_gk20a *f = &g->fifo; |
843 | u32 ret = 0; | 849 | u32 ret = 0; |
@@ -845,12 +851,9 @@ int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) | |||
845 | u32 mutex_ret = 0; | 851 | u32 mutex_ret = 0; |
846 | u32 runlist_id; | 852 | u32 runlist_id; |
847 | 853 | ||
848 | nvgpu_log_fn(g, "tsgid: %d", tsgid); | 854 | nvgpu_log_fn(g, "tsgid: %d", tsg->tsgid); |
849 | if (tsgid == FIFO_INVAL_TSG_ID) { | ||
850 | return 0; | ||
851 | } | ||
852 | 855 | ||
853 | runlist_id = f->tsg[tsgid].runlist_id; | 856 | runlist_id = tsg->runlist_id; |
854 | nvgpu_log_fn(g, "runlist_id: %d", runlist_id); | 857 | nvgpu_log_fn(g, "runlist_id: %d", runlist_id); |
855 | if (runlist_id == FIFO_INVAL_RUNLIST_ID) { | 858 | if (runlist_id == FIFO_INVAL_RUNLIST_ID) { |
856 | return 0; | 859 | return 0; |
@@ -859,27 +862,27 @@ int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) | |||
859 | nvgpu_mutex_acquire(&f->runlist_info[runlist_id].runlist_lock); | 862 | nvgpu_mutex_acquire(&f->runlist_info[runlist_id].runlist_lock); |
860 | 863 | ||
861 | /* WAR for Bug 2065990 */ | 864 | /* WAR for Bug 2065990 */ |
862 | gk20a_fifo_disable_tsg_sched(g, &f->tsg[tsgid]); | 865 | gk20a_fifo_disable_tsg_sched(g, tsg); |
863 | 866 | ||
864 | mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); | 867 | mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); |
865 | 868 | ||
866 | ret = __locked_fifo_preempt(g, tsgid, true); | 869 | ret = __locked_fifo_preempt(g, tsg->tsgid, true); |
867 | 870 | ||
868 | if (!mutex_ret) { | 871 | if (!mutex_ret) { |
869 | nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); | 872 | nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); |
870 | } | 873 | } |
871 | 874 | ||
872 | /* WAR for Bug 2065990 */ | 875 | /* WAR for Bug 2065990 */ |
873 | gk20a_fifo_enable_tsg_sched(g, &f->tsg[tsgid]); | 876 | gk20a_fifo_enable_tsg_sched(g, tsg); |
874 | 877 | ||
875 | nvgpu_mutex_release(&f->runlist_info[runlist_id].runlist_lock); | 878 | nvgpu_mutex_release(&f->runlist_info[runlist_id].runlist_lock); |
876 | 879 | ||
877 | if (ret) { | 880 | if (ret) { |
878 | if (nvgpu_platform_is_silicon(g)) { | 881 | if (nvgpu_platform_is_silicon(g)) { |
879 | nvgpu_err(g, "preempt timed out for tsgid: %u, " | 882 | nvgpu_err(g, "preempt timed out for tsgid: %u, " |
880 | "ctxsw timeout will trigger recovery if needed", tsgid); | 883 | "ctxsw timeout will trigger recovery if needed", tsg->tsgid); |
881 | } else { | 884 | } else { |
882 | gk20a_fifo_preempt_timeout_rc(g, tsgid, true); | 885 | gk20a_fifo_preempt_timeout_rc(g, tsg->tsgid, true); |
883 | } | 886 | } |
884 | } | 887 | } |
885 | 888 | ||