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path: root/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index b5af2972..5b84df47 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -982,6 +982,33 @@ static void gv11b_fifo_locked_abort_runlist_active_tsgs(struct gk20a *g,
982 } 982 }
983} 983}
984 984
985void gv11b_fifo_teardown_mask_intr(struct gk20a *g)
986{
987 u32 val;
988
989 /*
990 * ctxsw timeout error prevents recovery, and ctxsw error will retrigger
991 * every 100ms. Disable ctxsw timeout error to allow recovery.
992 */
993 val = gk20a_readl(g, fifo_intr_en_0_r());
994 val &= ~ fifo_intr_0_ctxsw_timeout_pending_f();
995 gk20a_writel(g, fifo_intr_en_0_r(), val);
996 gk20a_writel(g, fifo_intr_ctxsw_timeout_r(),
997 gk20a_readl(g, fifo_intr_ctxsw_timeout_r()));
998
999}
1000
1001void gv11b_fifo_teardown_unmask_intr(struct gk20a *g)
1002{
1003 u32 val;
1004
1005 /* enable ctxsw timeout interrupt */
1006 val = gk20a_readl(g, fifo_intr_en_0_r());
1007 val |= fifo_intr_0_ctxsw_timeout_pending_f();
1008 gk20a_writel(g, fifo_intr_en_0_r(), val);
1009}
1010
1011
985void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, 1012void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
986 u32 id, unsigned int id_type, unsigned int rc_type, 1013 u32 id, unsigned int id_type, unsigned int rc_type,
987 struct mmu_fault_info *mmfault) 1014 struct mmu_fault_info *mmfault)
@@ -1001,6 +1028,8 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
1001 runlist_lock); 1028 runlist_lock);
1002 } 1029 }
1003 1030
1031 g->ops.fifo.teardown_mask_intr(g);
1032
1004 /* get runlist id and tsg */ 1033 /* get runlist id and tsg */
1005 if (id_type == ID_TYPE_TSG) { 1034 if (id_type == ID_TYPE_TSG) {
1006 if (id != FIFO_INVAL_TSG_ID) { 1035 if (id != FIFO_INVAL_TSG_ID) {
@@ -1195,6 +1224,8 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
1195 nvgpu_pmu_enable_elpg(g); 1224 nvgpu_pmu_enable_elpg(g);
1196 } 1225 }
1197 1226
1227 g->ops.fifo.teardown_unmask_intr(g);
1228
1198 /* release runlist_lock */ 1229 /* release runlist_lock */
1199 if (runlist_id != FIFO_INVAL_RUNLIST_ID) { 1230 if (runlist_id != FIFO_INVAL_RUNLIST_ID) {
1200 nvgpu_log_fn(g, "release runlist_lock runlist_id = %d", 1231 nvgpu_log_fn(g, "release runlist_lock runlist_id = %d",