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path: root/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.c16
1 files changed, 10 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index a1f6d258..ace873e9 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -45,7 +45,6 @@
45#include "subctx_gv11b.h" 45#include "subctx_gv11b.h"
46#include "gr_gv11b.h" 46#include "gr_gv11b.h"
47 47
48#define CHANNEL_INFO_VEID0 0
49#define PBDMA_SUBDEVICE_ID 1 48#define PBDMA_SUBDEVICE_ID 1
50 49
51static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g, 50static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g,
@@ -94,7 +93,8 @@ static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist)
94 93
95 /* Time being use 0 pbdma sequencer */ 94 /* Time being use 0 pbdma sequencer */
96 runlist_entry = ram_rl_entry_type_channel_v() | 95 runlist_entry = ram_rl_entry_type_channel_v() |
97 ram_rl_entry_chan_runqueue_selector_f(0) | 96 ram_rl_entry_chan_runqueue_selector_f(
97 c->t19x.runqueue_sel) |
98 ram_rl_entry_chan_userd_target_f( 98 ram_rl_entry_chan_userd_target_f(
99 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) | 99 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) |
100 ram_rl_entry_chan_inst_target_f( 100 ram_rl_entry_chan_inst_target_f(
@@ -178,10 +178,14 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
178 178
179 nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); 179 nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid));
180 180
181 /* Until full subcontext is supported, always use VEID0 */ 181 if (c->t19x.subctx_id == CHANNEL_INFO_VEID0)
182 nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), 182 nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
183 pbdma_set_channel_info_scg_type_graphics_compute0_f() | 183 pbdma_set_channel_info_scg_type_graphics_compute0_f() |
184 pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0)); 184 pbdma_set_channel_info_veid_f(c->t19x.subctx_id));
185 else
186 nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
187 pbdma_set_channel_info_scg_type_compute1_f() |
188 pbdma_set_channel_info_veid_f(c->t19x.subctx_id));
185 189
186 gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); 190 gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem);
187 191