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path: root/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index 80bb64a0..1d5e593c 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -785,6 +785,21 @@ static int __locked_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask)
785 return ret; 785 return ret;
786} 786}
787 787
788/* TSG enable sequence applicable for Volta and onwards */
789int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg)
790{
791 struct gk20a *g = tsg->g;
792 struct channel_gk20a *ch;
793
794 down_read(&tsg->ch_list_lock);
795 nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
796 g->ops.fifo.enable_channel(ch);
797 }
798 up_read(&tsg->ch_list_lock);
799
800 return 0;
801}
802
788int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) 803int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid)
789{ 804{
790 struct fifo_gk20a *f = &g->fifo; 805 struct fifo_gk20a *f = &g->fifo;