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path: root/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index e9830c0e..7bb3d654 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -545,11 +545,11 @@ static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg)
545 struct gk20a *g = tsg->g; 545 struct gk20a *g = tsg->g;
546 struct channel_gk20a *ch; 546 struct channel_gk20a *ch;
547 547
548 down_read(&tsg->ch_list_lock); 548 nvgpu_rwsem_down_read(&tsg->ch_list_lock);
549 list_for_each_entry(ch, &tsg->ch_list, ch_entry) { 549 list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
550 gv11b_reset_eng_faulted_ch(g, ch->chid); 550 gv11b_reset_eng_faulted_ch(g, ch->chid);
551 } 551 }
552 up_read(&tsg->ch_list_lock); 552 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
553} 553}
554 554
555static void gv11b_reset_pbdma_faulted_ch(struct gk20a *g, u32 chid) 555static void gv11b_reset_pbdma_faulted_ch(struct gk20a *g, u32 chid)
@@ -566,11 +566,11 @@ static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg)
566 struct gk20a *g = tsg->g; 566 struct gk20a *g = tsg->g;
567 struct channel_gk20a *ch; 567 struct channel_gk20a *ch;
568 568
569 down_read(&tsg->ch_list_lock); 569 nvgpu_rwsem_down_read(&tsg->ch_list_lock);
570 list_for_each_entry(ch, &tsg->ch_list, ch_entry) { 570 list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
571 gv11b_reset_pbdma_faulted_ch(g, ch->chid); 571 gv11b_reset_pbdma_faulted_ch(g, ch->chid);
572 } 572 }
573 up_read(&tsg->ch_list_lock); 573 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
574} 574}
575 575
576void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, 576void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g,
@@ -799,11 +799,11 @@ int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg)
799 struct gk20a *g = tsg->g; 799 struct gk20a *g = tsg->g;
800 struct channel_gk20a *ch; 800 struct channel_gk20a *ch;
801 801
802 down_read(&tsg->ch_list_lock); 802 nvgpu_rwsem_down_read(&tsg->ch_list_lock);
803 nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) { 803 nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
804 g->ops.fifo.enable_channel(ch); 804 g->ops.fifo.enable_channel(ch);
805 } 805 }
806 up_read(&tsg->ch_list_lock); 806 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
807 807
808 return 0; 808 return 0;
809} 809}