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path: root/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fb_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fb_gv11b.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
index ce8f5669..bba7e66c 100644
--- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
@@ -935,12 +935,37 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g,
935 id = mmfault->chid; 935 id = mmfault->chid;
936 id_type = ID_TYPE_CHANNEL; 936 id_type = ID_TYPE_CHANNEL;
937 } 937 }
938 if (mmfault->refch->mmu_nack_handled) {
939 /* We have already recovered for the same
940 * context, skip doing another recovery.
941 */
942 mmfault->refch->mmu_nack_handled = false;
943 /*
944 * Recovery path can be entered twice for the
945 * same error in case of mmu nack. If mmu
946 * nack interrupt is handled before mmu fault
947 * then channel reference is increased to avoid
948 * closing the channel by userspace. Decrement
949 * channel reference.
950 */
951 gk20a_channel_put(mmfault->refch);
952 /* refch in mmfault is assigned at the time
953 * of copying fault info from snap reg or bar2
954 * fault buf.
955 */
956 gk20a_channel_put(mmfault->refch);
957 return;
958 }
938 } else { 959 } else {
939 id_type = ID_TYPE_UNKNOWN; 960 id_type = ID_TYPE_UNKNOWN;
940 } 961 }
941 if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) 962 if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID)
942 act_eng_bitmask = BIT(mmfault->faulted_engine); 963 act_eng_bitmask = BIT(mmfault->faulted_engine);
943 964
965 /* Indicate recovery is handled if mmu fault is a result of
966 * mmu nack.
967 */
968 mmfault->refch->mmu_nack_handled = true;
944 g->ops.fifo.teardown_ch_tsg(g, act_eng_bitmask, 969 g->ops.fifo.teardown_ch_tsg(g, act_eng_bitmask,
945 id, id_type, RC_TYPE_MMU_FAULT, mmfault); 970 id, id_type, RC_TYPE_MMU_FAULT, mmfault);
946 } else { 971 } else {