diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/ce_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c new file mode 100644 index 00000000..86518ac7 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c | |||
@@ -0,0 +1,110 @@ | |||
1 | /* | ||
2 | * Volta GPU series Copy Engine. | ||
3 | * | ||
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include "nvgpu/log.h" | ||
26 | #include "nvgpu/bitops.h" | ||
27 | |||
28 | #include "gk20a/gk20a.h" | ||
29 | |||
30 | #include "gp10b/ce_gp10b.h" | ||
31 | |||
32 | #include "ce_gv11b.h" | ||
33 | |||
34 | #include <nvgpu/hw/gv11b/hw_ce_gv11b.h> | ||
35 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> | ||
36 | |||
37 | u32 gv11b_ce_get_num_pce(struct gk20a *g) | ||
38 | { | ||
39 | /* register contains a bitmask indicating which physical copy | ||
40 | * engines are present (and not floorswept). | ||
41 | */ | ||
42 | u32 num_pce; | ||
43 | u32 ce_pce_map = gk20a_readl(g, ce_pce_map_r()); | ||
44 | |||
45 | num_pce = hweight32(ce_pce_map); | ||
46 | nvgpu_log_info(g, "num PCE: %d", num_pce); | ||
47 | return num_pce; | ||
48 | } | ||
49 | |||
50 | void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | ||
51 | { | ||
52 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); | ||
53 | u32 clear_intr = 0; | ||
54 | |||
55 | nvgpu_log(g, gpu_dbg_intr, "ce isr 0x%08x 0x%08x", ce_intr, inst_id); | ||
56 | |||
57 | /* An INVALID_CONFIG interrupt will be generated if a floorswept | ||
58 | * PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG | ||
59 | * registers. This is a fatal error and the LCE will have to be | ||
60 | * reset to get back to a working state. | ||
61 | */ | ||
62 | if (ce_intr & ce_intr_status_invalid_config_pending_f()) { | ||
63 | nvgpu_log(g, gpu_dbg_intr, | ||
64 | "ce: inst %d: invalid config", inst_id); | ||
65 | clear_intr |= ce_intr_status_invalid_config_reset_f(); | ||
66 | } | ||
67 | |||
68 | /* A MTHD_BUFFER_FAULT interrupt will be triggered if any access | ||
69 | * to a method buffer during context load or save encounters a fault. | ||
70 | * This is a fatal interrupt and will require at least the LCE to be | ||
71 | * reset before operations can start again, if not the entire GPU. | ||
72 | */ | ||
73 | if (ce_intr & ce_intr_status_mthd_buffer_fault_pending_f()) { | ||
74 | nvgpu_log(g, gpu_dbg_intr, | ||
75 | "ce: inst %d: mthd buffer fault", inst_id); | ||
76 | clear_intr |= ce_intr_status_mthd_buffer_fault_reset_f(); | ||
77 | } | ||
78 | |||
79 | gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr); | ||
80 | |||
81 | gp10b_ce_isr(g, inst_id, pri_base); | ||
82 | } | ||
83 | |||
84 | u32 gv11b_ce_get_num_lce(struct gk20a *g) | ||
85 | { | ||
86 | u32 reg_val, num_lce; | ||
87 | |||
88 | reg_val = gk20a_readl(g, top_num_ces_r()); | ||
89 | num_lce = top_num_ces_value_v(reg_val); | ||
90 | nvgpu_log_info(g, "num LCE: %d", num_lce); | ||
91 | |||
92 | return num_lce; | ||
93 | } | ||
94 | |||
95 | void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g) | ||
96 | { | ||
97 | u32 reg_val, num_lce, lce, clear_intr; | ||
98 | |||
99 | num_lce = gv11b_ce_get_num_lce(g); | ||
100 | |||
101 | for (lce = 0; lce < num_lce; lce++) { | ||
102 | reg_val = gk20a_readl(g, ce_intr_status_r(lce)); | ||
103 | if (reg_val & ce_intr_status_mthd_buffer_fault_pending_f()) { | ||
104 | nvgpu_log(g, gpu_dbg_intr, | ||
105 | "ce: lce %d: mthd buffer fault", lce); | ||
106 | clear_intr = ce_intr_status_mthd_buffer_fault_reset_f(); | ||
107 | gk20a_writel(g, ce_intr_status_r(lce), clear_intr); | ||
108 | } | ||
109 | } | ||
110 | } | ||