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path: root/drivers/gpu/nvgpu/gv11b/ce_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/ce_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/ce_gv11b.c11
1 files changed, 2 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c
index 9716c6d6..8bf636b1 100644
--- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c
@@ -28,7 +28,7 @@
28#include <nvgpu/hw/gv11b/hw_ce_gv11b.h> 28#include <nvgpu/hw/gv11b/hw_ce_gv11b.h>
29#include <nvgpu/hw/gv11b/hw_top_gv11b.h> 29#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
30 30
31static u32 gv11b_ce_get_num_pce(struct gk20a *g) 31u32 gv11b_ce_get_num_pce(struct gk20a *g)
32{ 32{
33 /* register contains a bitmask indicating which physical copy 33 /* register contains a bitmask indicating which physical copy
34 * engines are present (and not floorswept). 34 * engines are present (and not floorswept).
@@ -41,7 +41,7 @@ static u32 gv11b_ce_get_num_pce(struct gk20a *g)
41 return num_pce; 41 return num_pce;
42} 42}
43 43
44static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) 44void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
45{ 45{
46 u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); 46 u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
47 u32 clear_intr = 0; 47 u32 clear_intr = 0;
@@ -102,10 +102,3 @@ void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g)
102 } 102 }
103 } 103 }
104} 104}
105
106void gv11b_init_ce(struct gpu_ops *gops)
107{
108 gp10b_init_ce(gops);
109 gops->ce2.isr_stall = gv11b_ce_isr;
110 gops->ce2.get_num_pce = gv11b_ce_get_num_pce;
111}