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Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/acr_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/acr_gv11b.c294
1 files changed, 294 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
new file mode 100644
index 00000000..b245dbc6
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
@@ -0,0 +1,294 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifdef CONFIG_DEBUG_FS
24#include <linux/debugfs.h>
25#endif
26
27#include <nvgpu/types.h>
28#include <linux/platform/tegra/mc.h>
29
30#include <nvgpu/dma.h>
31#include <nvgpu/gmmu.h>
32#include <nvgpu/timers.h>
33#include <nvgpu/nvgpu_common.h>
34#include <nvgpu/kmem.h>
35#include <nvgpu/nvgpu_mem.h>
36#include <nvgpu/acr/nvgpu_acr.h>
37#include <nvgpu/firmware.h>
38#include <nvgpu/mm.h>
39
40#include "gk20a/gk20a.h"
41#include "acr_gv11b.h"
42#include "pmu_gv11b.h"
43#include "gk20a/pmu_gk20a.h"
44#include "gm20b/mm_gm20b.h"
45#include "gm20b/acr_gm20b.h"
46#include "gp106/acr_gp106.h"
47
48#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
49
50/*Defines*/
51#define gv11b_dbg_pmu(fmt, arg...) \
52 gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
53
54static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value)
55{
56 dma_addr->lo |= u64_lo32(value);
57 dma_addr->hi |= u64_hi32(value);
58}
59/*Externs*/
60
61/*Forwards*/
62
63/*Loads ACR bin to FB mem and bootstraps PMU with bootloader code
64 * start and end are addresses of ucode blob in non-WPR region*/
65int gv11b_bootstrap_hs_flcn(struct gk20a *g)
66{
67 struct mm_gk20a *mm = &g->mm;
68 struct vm_gk20a *vm = mm->pmu.vm;
69 int err = 0;
70 u64 *acr_dmem;
71 u32 img_size_in_bytes = 0;
72 u32 status, size, index;
73 u64 start;
74 struct acr_desc *acr = &g->acr;
75 struct nvgpu_firmware *acr_fw = acr->acr_fw;
76 struct flcn_bl_dmem_desc_v1 *bl_dmem_desc = &acr->bl_dmem_desc_v1;
77 u32 *acr_ucode_header_t210_load;
78 u32 *acr_ucode_data_t210_load;
79
80 start = nvgpu_mem_get_addr(g, &acr->ucode_blob);
81 size = acr->ucode_blob.size;
82
83 gv11b_dbg_pmu("acr ucode blob start %llx\n", start);
84 gv11b_dbg_pmu("acr ucode blob size %x\n", size);
85
86 gv11b_dbg_pmu("");
87
88 if (!acr_fw) {
89 /*First time init case*/
90 acr_fw = nvgpu_request_firmware(g,
91 GM20B_HSBIN_PMU_UCODE_IMAGE, 0);
92 if (!acr_fw) {
93 nvgpu_err(g, "pmu ucode get fail");
94 return -ENOENT;
95 }
96 acr->acr_fw = acr_fw;
97 acr->hsbin_hdr = (struct bin_hdr *)acr_fw->data;
98 acr->fw_hdr = (struct acr_fw_header *)(acr_fw->data +
99 acr->hsbin_hdr->header_offset);
100 acr_ucode_data_t210_load = (u32 *)(acr_fw->data +
101 acr->hsbin_hdr->data_offset);
102 acr_ucode_header_t210_load = (u32 *)(acr_fw->data +
103 acr->fw_hdr->hdr_offset);
104 img_size_in_bytes = ALIGN((acr->hsbin_hdr->data_size), 256);
105
106 gv11b_dbg_pmu("sig dbg offset %u\n",
107 acr->fw_hdr->sig_dbg_offset);
108 gv11b_dbg_pmu("sig dbg size %u\n", acr->fw_hdr->sig_dbg_size);
109 gv11b_dbg_pmu("sig prod offset %u\n",
110 acr->fw_hdr->sig_prod_offset);
111 gv11b_dbg_pmu("sig prod size %u\n",
112 acr->fw_hdr->sig_prod_size);
113 gv11b_dbg_pmu("patch loc %u\n", acr->fw_hdr->patch_loc);
114 gv11b_dbg_pmu("patch sig %u\n", acr->fw_hdr->patch_sig);
115 gv11b_dbg_pmu("header offset %u\n", acr->fw_hdr->hdr_offset);
116 gv11b_dbg_pmu("header size %u\n", acr->fw_hdr->hdr_size);
117
118 /* Lets patch the signatures first.. */
119 if (acr_ucode_patch_sig(g, acr_ucode_data_t210_load,
120 (u32 *)(acr_fw->data +
121 acr->fw_hdr->sig_prod_offset),
122 (u32 *)(acr_fw->data +
123 acr->fw_hdr->sig_dbg_offset),
124 (u32 *)(acr_fw->data +
125 acr->fw_hdr->patch_loc),
126 (u32 *)(acr_fw->data +
127 acr->fw_hdr->patch_sig)) < 0) {
128 nvgpu_err(g, "patch signatures fail");
129 err = -1;
130 goto err_release_acr_fw;
131 }
132 err = nvgpu_dma_alloc_map_sys(vm, img_size_in_bytes,
133 &acr->acr_ucode);
134 if (err) {
135 err = -ENOMEM;
136 goto err_release_acr_fw;
137 }
138
139 for (index = 0; index < 9; index++)
140 gv11b_dbg_pmu("acr_ucode_header_t210_load %u\n",
141 acr_ucode_header_t210_load[index]);
142
143 acr_dmem = (u64 *)
144 &(((u8 *)acr_ucode_data_t210_load)[
145 acr_ucode_header_t210_load[2]]);
146 acr->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *)((u8 *)(
147 acr->acr_ucode.cpu_va) + acr_ucode_header_t210_load[2]);
148 ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_start =
149 (start);
150 ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_size =
151 size;
152 ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.no_regions = 2;
153 ((struct flcn_acr_desc_v1 *)acr_dmem)->wpr_offset = 0;
154
155 nvgpu_mem_wr_n(g, &acr->acr_ucode, 0,
156 acr_ucode_data_t210_load, img_size_in_bytes);
157 /*
158 * In order to execute this binary, we will be using
159 * a bootloader which will load this image into PMU IMEM/DMEM.
160 * Fill up the bootloader descriptor for PMU HAL to use..
161 * TODO: Use standard descriptor which the generic bootloader is
162 * checked in.
163 */
164 bl_dmem_desc->signature[0] = 0;
165 bl_dmem_desc->signature[1] = 0;
166 bl_dmem_desc->signature[2] = 0;
167 bl_dmem_desc->signature[3] = 0;
168 bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
169 flcn64_set_dma(&bl_dmem_desc->code_dma_base,
170 acr->acr_ucode.gpu_va);
171 bl_dmem_desc->non_sec_code_off = acr_ucode_header_t210_load[0];
172 bl_dmem_desc->non_sec_code_size = acr_ucode_header_t210_load[1];
173 bl_dmem_desc->sec_code_off = acr_ucode_header_t210_load[5];
174 bl_dmem_desc->sec_code_size = acr_ucode_header_t210_load[6];
175 bl_dmem_desc->code_entry_point = 0; /* Start at 0th offset */
176 flcn64_set_dma(&bl_dmem_desc->data_dma_base,
177 acr->acr_ucode.gpu_va +
178 acr_ucode_header_t210_load[2]);
179 bl_dmem_desc->data_size = acr_ucode_header_t210_load[3];
180 } else
181 acr->acr_dmem_desc_v1->nonwpr_ucode_blob_size = 0;
182 status = pmu_exec_gen_bl(g, bl_dmem_desc, 1);
183 if (status != 0) {
184 err = status;
185 goto err_free_ucode_map;
186 }
187
188 return 0;
189err_free_ucode_map:
190 nvgpu_dma_unmap_free(vm, &acr->acr_ucode);
191err_release_acr_fw:
192 nvgpu_release_firmware(g, acr_fw);
193 acr->acr_fw = NULL;
194
195 return err;
196}
197
198static int bl_bootstrap(struct nvgpu_pmu *pmu,
199 struct flcn_bl_dmem_desc_v1 *pbl_desc, u32 bl_sz)
200{
201 struct gk20a *g = gk20a_from_pmu(pmu);
202 struct acr_desc *acr = &g->acr;
203 struct mm_gk20a *mm = &g->mm;
204 u32 virt_addr = 0;
205 struct hsflcn_bl_desc *pmu_bl_gm10x_desc = g->acr.pmu_hsbl_desc;
206 u32 dst;
207
208 gk20a_dbg_fn("");
209
210 gk20a_writel(g, pwr_falcon_itfen_r(),
211 gk20a_readl(g, pwr_falcon_itfen_r()) |
212 pwr_falcon_itfen_ctxen_enable_f());
213 gk20a_writel(g, pwr_pmu_new_instblk_r(),
214 pwr_pmu_new_instblk_ptr_f(
215 nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
216 pwr_pmu_new_instblk_valid_f(1) |
217 pwr_pmu_new_instblk_target_sys_ncoh_f());
218
219 /*copy bootloader interface structure to dmem*/
220 nvgpu_flcn_copy_to_dmem(pmu->flcn, 0, (u8 *)pbl_desc,
221 sizeof(struct flcn_bl_dmem_desc_v1), 0);
222
223 /* copy bootloader to TOP of IMEM */
224 dst = (pwr_falcon_hwcfg_imem_size_v(
225 gk20a_readl(g, pwr_falcon_hwcfg_r())) << 8) - bl_sz;
226
227 nvgpu_flcn_copy_to_imem(pmu->flcn, dst,
228 (u8 *)(acr->hsbl_ucode.cpu_va), bl_sz, 0, 0,
229 pmu_bl_gm10x_desc->bl_start_tag);
230
231 gv11b_dbg_pmu("Before starting falcon with BL\n");
232
233 virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8;
234
235 nvgpu_flcn_bootstrap(pmu->flcn, virt_addr);
236
237 return 0;
238}
239
240int gv11b_init_pmu_setup_hw1(struct gk20a *g,
241 void *desc, u32 bl_sz)
242{
243
244 struct nvgpu_pmu *pmu = &g->pmu;
245 int err;
246
247 gk20a_dbg_fn("");
248
249 nvgpu_mutex_acquire(&pmu->isr_mutex);
250 nvgpu_flcn_reset(pmu->flcn);
251 pmu->isr_enabled = true;
252 nvgpu_mutex_release(&pmu->isr_mutex);
253
254 /* setup apertures - virtual */
255 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
256 pwr_fbif_transcfg_mem_type_physical_f() |
257 pwr_fbif_transcfg_target_noncoherent_sysmem_f());
258 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
259 pwr_fbif_transcfg_mem_type_virtual_f());
260 /* setup apertures - physical */
261 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
262 pwr_fbif_transcfg_mem_type_physical_f() |
263 pwr_fbif_transcfg_target_noncoherent_sysmem_f());
264 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
265 pwr_fbif_transcfg_mem_type_physical_f() |
266 pwr_fbif_transcfg_target_coherent_sysmem_f());
267 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
268 pwr_fbif_transcfg_mem_type_physical_f() |
269 pwr_fbif_transcfg_target_noncoherent_sysmem_f());
270
271 /*Copying pmu cmdline args*/
272 g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
273 g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
274 g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
275 g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
276 pmu, GK20A_PMU_TRACE_BUFSIZE);
277 g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu);
278 g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx(
279 pmu, GK20A_PMU_DMAIDX_VIRT);
280 nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args,
281 (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
282 g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
283 /*disable irqs for hs falcon booting as we will poll for halt*/
284 nvgpu_mutex_acquire(&pmu->isr_mutex);
285 pmu_enable_irq(pmu, false);
286 pmu->isr_enabled = false;
287 nvgpu_mutex_release(&pmu->isr_mutex);
288 /*Clearing mailbox register used to reflect capabilities*/
289 gk20a_writel(g, pwr_falcon_mailbox1_r(), 0);
290 err = bl_bootstrap(pmu, desc, bl_sz);
291 if (err)
292 return err;
293 return 0;
294}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-15 23:53:44 -0400