diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/acr_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/acr_gv11b.c | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c index f5ca144a..de2502ce 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c | |||
@@ -38,6 +38,7 @@ | |||
38 | #include "acr_gv11b.h" | 38 | #include "acr_gv11b.h" |
39 | #include "pmu_gv11b.h" | 39 | #include "pmu_gv11b.h" |
40 | #include "gm20b/mm_gm20b.h" | 40 | #include "gm20b/mm_gm20b.h" |
41 | #include "gm20b/pmu_gm20b.h" | ||
41 | #include "gm20b/acr_gm20b.h" | 42 | #include "gm20b/acr_gm20b.h" |
42 | #include "gp106/acr_gp106.h" | 43 | #include "gp106/acr_gp106.h" |
43 | 44 | ||
@@ -68,6 +69,8 @@ void gv11b_setup_apertures(struct gk20a *g) | |||
68 | struct mm_gk20a *mm = &g->mm; | 69 | struct mm_gk20a *mm = &g->mm; |
69 | struct nvgpu_mem *inst_block = &mm->pmu.inst_block; | 70 | struct nvgpu_mem *inst_block = &mm->pmu.inst_block; |
70 | 71 | ||
72 | nvgpu_log_fn(g, " "); | ||
73 | |||
71 | /* setup apertures - virtual */ | 74 | /* setup apertures - virtual */ |
72 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | 75 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), |
73 | pwr_fbif_transcfg_mem_type_physical_f() | | 76 | pwr_fbif_transcfg_mem_type_physical_f() | |
@@ -91,3 +94,87 @@ void gv11b_setup_apertures(struct gk20a *g) | |||
91 | pwr_fbif_transcfg_mem_type_physical_f() | | 94 | pwr_fbif_transcfg_mem_type_physical_f() | |
92 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | 95 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); |
93 | } | 96 | } |
97 | |||
98 | int gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr, | ||
99 | struct hs_acr *acr_desc, bool is_recovery) | ||
100 | { | ||
101 | struct nvgpu_firmware *acr_fw = acr_desc->acr_fw; | ||
102 | struct acr_fw_header *acr_fw_hdr = NULL; | ||
103 | struct bin_hdr *acr_fw_bin_hdr = NULL; | ||
104 | struct flcn_acr_desc_v1 *acr_dmem_desc; | ||
105 | u32 *acr_ucode_header = NULL; | ||
106 | u32 *acr_ucode_data = NULL; | ||
107 | |||
108 | nvgpu_log_fn(g, " "); | ||
109 | |||
110 | if (is_recovery) { | ||
111 | acr_desc->acr_dmem_desc_v1->nonwpr_ucode_blob_size = 0U; | ||
112 | } else { | ||
113 | acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data; | ||
114 | acr_fw_hdr = (struct acr_fw_header *) | ||
115 | (acr_fw->data + acr_fw_bin_hdr->header_offset); | ||
116 | |||
117 | acr_ucode_data = (u32 *)(acr_fw->data + | ||
118 | acr_fw_bin_hdr->data_offset); | ||
119 | acr_ucode_header = (u32 *)(acr_fw->data + | ||
120 | acr_fw_hdr->hdr_offset); | ||
121 | |||
122 | /* During recovery need to update blob size as 0x0*/ | ||
123 | acr_desc->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *) | ||
124 | ((u8 *)(acr_desc->acr_ucode.cpu_va) + | ||
125 | acr_ucode_header[2U]); | ||
126 | |||
127 | /* Patch WPR info to ucode */ | ||
128 | acr_dmem_desc = (struct flcn_acr_desc_v1 *) | ||
129 | &(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]); | ||
130 | |||
131 | acr_dmem_desc->nonwpr_ucode_blob_start = | ||
132 | nvgpu_mem_get_addr(g, &g->acr.ucode_blob); | ||
133 | acr_dmem_desc->nonwpr_ucode_blob_size = | ||
134 | g->acr.ucode_blob.size; | ||
135 | acr_dmem_desc->regions.no_regions = 1U; | ||
136 | acr_dmem_desc->wpr_offset = 0U; | ||
137 | } | ||
138 | |||
139 | return 0; | ||
140 | } | ||
141 | |||
142 | static void gv11b_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr) | ||
143 | { | ||
144 | struct hs_flcn_bl *hs_bl = &hs_acr->acr_hs_bl; | ||
145 | |||
146 | nvgpu_log_fn(g, " "); | ||
147 | |||
148 | hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE; | ||
149 | |||
150 | hs_acr->acr_type = ACR_DEFAULT; | ||
151 | hs_acr->acr_fw_name = HSBIN_ACR_UCODE_IMAGE; | ||
152 | |||
153 | hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc_v1; | ||
154 | hs_acr->bl_dmem_desc_size = sizeof(struct flcn_bl_dmem_desc_v1); | ||
155 | |||
156 | hs_acr->acr_flcn = &g->pmu_flcn; | ||
157 | hs_acr->acr_flcn_setup_hw_and_bl_bootstrap = | ||
158 | gm20b_pmu_setup_hw_and_bl_bootstrap; | ||
159 | } | ||
160 | |||
161 | void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) | ||
162 | { | ||
163 | nvgpu_log_fn(g, " "); | ||
164 | |||
165 | acr->g = g; | ||
166 | |||
167 | acr->bootstrap_owner = LSF_FALCON_ID_PMU; | ||
168 | acr->max_supported_lsfm = MAX_SUPPORTED_LSFM; | ||
169 | |||
170 | gv11b_acr_default_sw_init(g, &acr->acr); | ||
171 | |||
172 | acr->get_wpr_info = gm20b_wpr_info; | ||
173 | acr->alloc_blob_space = gv11b_alloc_blob_space; | ||
174 | acr->bootstrap_hs_acr = gm20b_bootstrap_hs_acr; | ||
175 | acr->patch_wpr_info_to_ucode = gv11b_acr_patch_wpr_info_to_ucode; | ||
176 | acr->acr_fill_bl_dmem_desc = | ||
177 | gp106_acr_fill_bl_dmem_desc; | ||
178 | |||
179 | acr->remove_support = gm20b_remove_acr_support; | ||
180 | } | ||