diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/mc_gv100.c | 4 |
2 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index a4dd09ec..23a3d78f 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -464,6 +464,8 @@ static const struct gpu_ops gv100_ops = { | |||
464 | .mem_unlock = gv100_fb_memory_unlock, | 464 | .mem_unlock = gv100_fb_memory_unlock, |
465 | .init_nvlink = gv100_fb_init_nvlink, | 465 | .init_nvlink = gv100_fb_init_nvlink, |
466 | .enable_nvlink = gv100_fb_enable_nvlink, | 466 | .enable_nvlink = gv100_fb_enable_nvlink, |
467 | .enable_hub_intr = gv11b_fb_enable_hub_intr, | ||
468 | .disable_hub_intr = gv11b_fb_disable_hub_intr, | ||
467 | }, | 469 | }, |
468 | .clock_gating = { | 470 | .clock_gating = { |
469 | .slcg_bus_load_gating_prod = | 471 | .slcg_bus_load_gating_prod = |
diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.c b/drivers/gpu/nvgpu/gv100/mc_gv100.c index 31dc97d9..7ed9e6da 100644 --- a/drivers/gpu/nvgpu/gv100/mc_gv100.c +++ b/drivers/gpu/nvgpu/gv100/mc_gv100.c | |||
@@ -41,7 +41,7 @@ void mc_gv100_intr_enable(struct gk20a *g) | |||
41 | 0xffffffffU); | 41 | 0xffffffffU); |
42 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), | 42 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), |
43 | 0xffffffffU); | 43 | 0xffffffffU); |
44 | gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); | 44 | g->ops.fb.disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); |
45 | 45 | ||
46 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = | 46 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = |
47 | mc_intr_pfifo_pending_f() | | 47 | mc_intr_pfifo_pending_f() | |
@@ -57,7 +57,7 @@ void mc_gv100_intr_enable(struct gk20a *g) | |||
57 | | eng_intr_mask; | 57 | | eng_intr_mask; |
58 | 58 | ||
59 | /* TODO: Enable PRI faults for HUB ECC err intr */ | 59 | /* TODO: Enable PRI faults for HUB ECC err intr */ |
60 | gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types); | 60 | g->ops.fb.enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types); |
61 | 61 | ||
62 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | 62 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), |
63 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); | 63 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); |