diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gr_gv100.c | 44 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gr_gv100.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 |
3 files changed, 51 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index bf143dbb..3aed7a19 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c | |||
@@ -34,6 +34,8 @@ | |||
34 | 34 | ||
35 | #include <nvgpu/hw/gv100/hw_gr_gv100.h> | 35 | #include <nvgpu/hw/gv100/hw_gr_gv100.h> |
36 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> | 36 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> |
37 | #include <nvgpu/hw/gv100/hw_fuse_gv100.h> | ||
38 | |||
37 | 39 | ||
38 | /* | 40 | /* |
39 | * Estimate performance if the given logical TPC in the given logical GPC were | 41 | * Estimate performance if the given logical TPC in the given logical GPC were |
@@ -329,3 +331,45 @@ u32 gr_gv100_get_patch_slots(struct gk20a *g) | |||
329 | 331 | ||
330 | return size; | 332 | return size; |
331 | } | 333 | } |
334 | |||
335 | int gr_gv100_add_ctxsw_reg_pm_fbpa(struct gk20a *g, | ||
336 | struct ctxsw_buf_offset_map_entry *map, | ||
337 | struct aiv_list_gk20a *regs, | ||
338 | u32 *count, u32 *offset, | ||
339 | u32 max_cnt, u32 base, | ||
340 | u32 num_fbpas, u32 stride, u32 mask) | ||
341 | { | ||
342 | u32 fbpa_id; | ||
343 | u32 idx; | ||
344 | u32 cnt = *count; | ||
345 | u32 off = *offset; | ||
346 | u32 active_fbpa_mask; | ||
347 | |||
348 | if ((cnt + (regs->count * num_fbpas)) > max_cnt) | ||
349 | return -EINVAL; | ||
350 | |||
351 | /* | ||
352 | * Read active fbpa mask from fuse | ||
353 | * Note that 0:enable and 1:disable in value read from fuse so we've to | ||
354 | * flip the bits. | ||
355 | * Also set unused bits to zero | ||
356 | */ | ||
357 | active_fbpa_mask = nvgpu_readl(g, fuse_status_opt_fbio_r()); | ||
358 | active_fbpa_mask = ~active_fbpa_mask; | ||
359 | active_fbpa_mask = active_fbpa_mask & ((1 << num_fbpas) - 1); | ||
360 | |||
361 | for (idx = 0; idx < regs->count; idx++) { | ||
362 | for (fbpa_id = 0; fbpa_id < num_fbpas; fbpa_id++) { | ||
363 | if (active_fbpa_mask & BIT(fbpa_id)) { | ||
364 | map[cnt].addr = base + | ||
365 | (regs->l[idx].addr & mask) + | ||
366 | (fbpa_id * stride); | ||
367 | map[cnt++].offset = off; | ||
368 | off += 4; | ||
369 | } | ||
370 | } | ||
371 | } | ||
372 | *count = cnt; | ||
373 | *offset = off; | ||
374 | return 0; | ||
375 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h index 690bba57..e1174686 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h | |||
@@ -33,4 +33,10 @@ void gr_gv100_program_sm_id_numbering(struct gk20a *g, | |||
33 | u32 gpc, u32 tpc, u32 smid); | 33 | u32 gpc, u32 tpc, u32 smid); |
34 | int gr_gv100_load_smid_config(struct gk20a *g); | 34 | int gr_gv100_load_smid_config(struct gk20a *g); |
35 | u32 gr_gv100_get_patch_slots(struct gk20a *g); | 35 | u32 gr_gv100_get_patch_slots(struct gk20a *g); |
36 | int gr_gv100_add_ctxsw_reg_pm_fbpa(struct gk20a *g, | ||
37 | struct ctxsw_buf_offset_map_entry *map, | ||
38 | struct aiv_list_gk20a *regs, | ||
39 | u32 *count, u32 *offset, | ||
40 | u32 max_cnt, u32 base, | ||
41 | u32 num_fbpas, u32 stride, u32 mask); | ||
36 | #endif | 42 | #endif |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 3dbd1e01..08fc7c34 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -429,6 +429,7 @@ static const struct gpu_ops gv100_ops = { | |||
429 | .set_error_notifier = gk20a_gr_set_error_notifier, | 429 | .set_error_notifier = gk20a_gr_set_error_notifier, |
430 | .handle_notify_pending = gk20a_gr_handle_notify_pending, | 430 | .handle_notify_pending = gk20a_gr_handle_notify_pending, |
431 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, | 431 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, |
432 | .add_ctxsw_reg_pm_fbpa = gr_gv100_add_ctxsw_reg_pm_fbpa, | ||
432 | }, | 433 | }, |
433 | .fb = { | 434 | .fb = { |
434 | .reset = gv100_fb_reset, | 435 | .reset = gv100_fb_reset, |