diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/fifo_gv100.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/fifo_gv100.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/mm_gv100.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/mm_gv100.h | 1 |
5 files changed, 27 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.c b/drivers/gpu/nvgpu/gv100/fifo_gv100.c index e19301e6..79862f6b 100644 --- a/drivers/gpu/nvgpu/gv100/fifo_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.c | |||
@@ -26,7 +26,15 @@ | |||
26 | 26 | ||
27 | #include <nvgpu/hw/gv100/hw_ccsr_gv100.h> | 27 | #include <nvgpu/hw/gv100/hw_ccsr_gv100.h> |
28 | 28 | ||
29 | #define DEFAULT_FIFO_PREEMPT_TIMEOUT 0x3FFFFFUL | ||
30 | |||
29 | u32 gv100_fifo_get_num_fifos(struct gk20a *g) | 31 | u32 gv100_fifo_get_num_fifos(struct gk20a *g) |
30 | { | 32 | { |
31 | return ccsr_channel__size_1_v(); | 33 | return ccsr_channel__size_1_v(); |
32 | } | 34 | } |
35 | |||
36 | u32 gv100_fifo_get_preempt_timeout(struct gk20a *g) | ||
37 | { | ||
38 | return DEFAULT_FIFO_PREEMPT_TIMEOUT; | ||
39 | } | ||
40 | |||
diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.h b/drivers/gpu/nvgpu/gv100/fifo_gv100.h index 3ffb417c..af6ad030 100644 --- a/drivers/gpu/nvgpu/gv100/fifo_gv100.h +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.h | |||
@@ -29,4 +29,5 @@ | |||
29 | struct gk20a; | 29 | struct gk20a; |
30 | 30 | ||
31 | u32 gv100_fifo_get_num_fifos(struct gk20a *g); | 31 | u32 gv100_fifo_get_num_fifos(struct gk20a *g); |
32 | u32 gv100_fifo_get_preempt_timeout(struct gk20a *g); | ||
32 | #endif | 33 | #endif |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 4e05f22b..ff852168 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -424,6 +424,7 @@ static const struct gpu_ops gv100_ops = { | |||
424 | .mem_unlock = gv100_fb_memory_unlock, | 424 | .mem_unlock = gv100_fb_memory_unlock, |
425 | }, | 425 | }, |
426 | .fifo = { | 426 | .fifo = { |
427 | .get_preempt_timeout = gv100_fifo_get_preempt_timeout, | ||
427 | .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, | 428 | .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, |
428 | .bind_channel = channel_gm20b_bind, | 429 | .bind_channel = channel_gm20b_bind, |
429 | .unbind_channel = channel_gv11b_unbind, | 430 | .unbind_channel = channel_gv11b_unbind, |
@@ -470,7 +471,7 @@ static const struct gpu_ops gv100_ops = { | |||
470 | .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, | 471 | .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, |
471 | .is_preempt_pending = gv11b_fifo_is_preempt_pending, | 472 | .is_preempt_pending = gv11b_fifo_is_preempt_pending, |
472 | .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, | 473 | .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, |
473 | .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, | 474 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, |
474 | .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, | 475 | .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, |
475 | .handle_sched_error = gv11b_fifo_handle_sched_error, | 476 | .handle_sched_error = gv11b_fifo_handle_sched_error, |
476 | .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, | 477 | .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, |
@@ -523,7 +524,7 @@ static const struct gpu_ops gv100_ops = { | |||
523 | .vm_bind_channel = gk20a_vm_bind_channel, | 524 | .vm_bind_channel = gk20a_vm_bind_channel, |
524 | .fb_flush = gk20a_mm_fb_flush, | 525 | .fb_flush = gk20a_mm_fb_flush, |
525 | .l2_invalidate = gk20a_mm_l2_invalidate, | 526 | .l2_invalidate = gk20a_mm_l2_invalidate, |
526 | .l2_flush = gv11b_mm_l2_flush, | 527 | .l2_flush = gk20a_mm_l2_flush, |
527 | .cbc_clean = gk20a_mm_cbc_clean, | 528 | .cbc_clean = gk20a_mm_cbc_clean, |
528 | .set_big_page_size = gm20b_mm_set_big_page_size, | 529 | .set_big_page_size = gm20b_mm_set_big_page_size, |
529 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | 530 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, |
@@ -542,6 +543,7 @@ static const struct gpu_ops gv100_ops = { | |||
542 | .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, | 543 | .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, |
543 | .remove_bar2_vm = gv11b_mm_remove_bar2_vm, | 544 | .remove_bar2_vm = gv11b_mm_remove_bar2_vm, |
544 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, | 545 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, |
546 | .get_flush_retries = gv100_mm_get_flush_retries, | ||
545 | }, | 547 | }, |
546 | .pramin = { | 548 | .pramin = { |
547 | .enter = gk20a_pramin_enter, | 549 | .enter = gk20a_pramin_enter, |
diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c index 93688206..1b46faae 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.c +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c | |||
@@ -40,3 +40,16 @@ size_t gv100_mm_get_vidmem_size(struct gk20a *g) | |||
40 | 40 | ||
41 | return bytes; | 41 | return bytes; |
42 | } | 42 | } |
43 | |||
44 | u32 gv100_mm_get_flush_retries(struct gk20a *g, enum nvgpu_flush_op op) | ||
45 | { | ||
46 | switch (op) { | ||
47 | /* GV100 has a large FB so it needs larger timeouts */ | ||
48 | case NVGPU_FLUSH_FB: | ||
49 | return 2000; | ||
50 | case NVGPU_FLUSH_L2_FLUSH: | ||
51 | return 2000; | ||
52 | default: | ||
53 | return 200; /* Default retry timer */ | ||
54 | } | ||
55 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h index eba724f9..ea896503 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.h +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h | |||
@@ -28,5 +28,6 @@ | |||
28 | struct gk20a; | 28 | struct gk20a; |
29 | 29 | ||
30 | size_t gv100_mm_get_vidmem_size(struct gk20a *g); | 30 | size_t gv100_mm_get_vidmem_size(struct gk20a *g); |
31 | u32 gv100_mm_get_flush_retries(struct gk20a *g, enum nvgpu_flush_op op); | ||
31 | 32 | ||
32 | #endif | 33 | #endif |