diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/perf_gv100.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/perf_gv100.c | 120 |
1 files changed, 120 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv100/perf_gv100.c b/drivers/gpu/nvgpu/gv100/perf_gv100.c new file mode 100644 index 00000000..f3ba78ba --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/perf_gv100.c | |||
@@ -0,0 +1,120 @@ | |||
1 | /* | ||
2 | * GV100 PERF | ||
3 | * | ||
4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/pmu.h> | ||
26 | #include <nvgpu/bug.h> | ||
27 | |||
28 | #include "gk20a/gk20a.h" | ||
29 | #include "gv100/perf_gv100.h" | ||
30 | |||
31 | static int pmu_set_boot_clk_runcb_fn(void *arg) | ||
32 | { | ||
33 | struct gk20a *g = (struct gk20a *)arg; | ||
34 | struct nvgpu_pmu *pmu = &g->pmu; | ||
35 | struct nv_pmu_rpc_struct_perf_load rpc; | ||
36 | struct perf_pmupstate *perf_pmu = &g->perf_pmu; | ||
37 | struct nvgpu_vfe_invalidate *vfe_init = &perf_pmu->vfe_init; | ||
38 | int status = 0; | ||
39 | |||
40 | nvgpu_log_fn(g, "thread start"); | ||
41 | |||
42 | while (true) { | ||
43 | NVGPU_COND_WAIT_INTERRUPTIBLE(&vfe_init->wq, | ||
44 | (vfe_init->state_change == true), 0); | ||
45 | |||
46 | vfe_init->state_change = false; | ||
47 | |||
48 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perf_load)); | ||
49 | PMU_RPC_EXECUTE_CPB(status, pmu, PERF, VFE_INVALIDATE, &rpc, 0); | ||
50 | if (status != 0) { | ||
51 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
52 | status); | ||
53 | } | ||
54 | status = nvgpu_clk_set_fll_clk_gv10x(g); | ||
55 | } | ||
56 | |||
57 | return 0; | ||
58 | } | ||
59 | |||
60 | static int gv100_pmu_handle_perf_event(struct gk20a *g, void *pmumsg) | ||
61 | { | ||
62 | struct nv_pmu_perf_msg *msg = (struct nv_pmu_perf_msg *)pmumsg; | ||
63 | struct perf_pmupstate *perf_pmu = &g->perf_pmu; | ||
64 | |||
65 | nvgpu_log_fn(g, " "); | ||
66 | switch (msg->msg_type) { | ||
67 | case NV_PMU_PERF_MSG_ID_VFE_CALLBACK: | ||
68 | perf_pmu->vfe_init.state_change = true; | ||
69 | nvgpu_cond_signal(&perf_pmu->vfe_init.wq); | ||
70 | break; | ||
71 | default: | ||
72 | WARN_ON(1); | ||
73 | break; | ||
74 | } | ||
75 | return 0; | ||
76 | } | ||
77 | |||
78 | u32 perf_pmu_init_vfe_perf_event(struct gk20a *g) | ||
79 | { | ||
80 | struct perf_pmupstate *perf_pmu = &g->perf_pmu; | ||
81 | char thread_name[64]; | ||
82 | u32 err = 0; | ||
83 | |||
84 | nvgpu_log_fn(g, " "); | ||
85 | |||
86 | nvgpu_cond_init(&perf_pmu->vfe_init.wq); | ||
87 | |||
88 | snprintf(thread_name, sizeof(thread_name), | ||
89 | "nvgpu_vfe_invalidate_init_%s", g->name); | ||
90 | |||
91 | err = nvgpu_thread_create(&perf_pmu->vfe_init.state_task, g, | ||
92 | pmu_set_boot_clk_runcb_fn, thread_name); | ||
93 | if (err != 0U) { | ||
94 | nvgpu_err(g, "failed to start nvgpu_vfe_invalidate_init thread"); | ||
95 | } | ||
96 | |||
97 | return err; | ||
98 | |||
99 | } | ||
100 | |||
101 | u32 gv100_perf_pmu_vfe_load(struct gk20a *g) | ||
102 | { | ||
103 | struct nvgpu_pmu *pmu = &g->pmu; | ||
104 | struct nv_pmu_rpc_struct_perf_load rpc; | ||
105 | u32 status = 0; | ||
106 | |||
107 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perf_load)); | ||
108 | PMU_RPC_EXECUTE_CPB(status, pmu, PERF, VFE_INVALIDATE, &rpc, 0); | ||
109 | if (status != 0U) { | ||
110 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
111 | status); | ||
112 | } | ||
113 | |||
114 | perf_pmu_init_vfe_perf_event(g); | ||
115 | |||
116 | /*register call back for future VFE updates*/ | ||
117 | g->ops.perf.handle_pmu_perf_event = gv100_pmu_handle_perf_event; | ||
118 | |||
119 | return status; | ||
120 | } | ||