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path: root/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gv100/nvlink_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/nvlink_gv100.c78
1 files changed, 29 insertions, 49 deletions
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
index df948301..0ad45540 100644
--- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
@@ -2115,9 +2115,10 @@ int gv100_nvlink_discover_ioctrl(struct gk20a *g)
2115 struct nvgpu_nvlink_ioctrl_list *ioctrl_table; 2115 struct nvgpu_nvlink_ioctrl_list *ioctrl_table;
2116 u32 table_entry; 2116 u32 table_entry;
2117 u32 devinfo_type; 2117 u32 devinfo_type;
2118 bool is_ioctrl = false;
2119 bool is_chain = false;
2120 u32 io_num_entries = 0; 2118 u32 io_num_entries = 0;
2119 u32 entry_engine = 0;
2120 u32 entry_enum = 0;
2121 u32 entry_data = 0;
2121 2122
2122 ioctrl_table = nvgpu_kzalloc(g, top_device_info__size_1_v() * 2123 ioctrl_table = nvgpu_kzalloc(g, top_device_info__size_1_v() *
2123 sizeof(struct nvgpu_nvlink_ioctrl_list)); 2124 sizeof(struct nvgpu_nvlink_ioctrl_list));
@@ -2126,64 +2127,44 @@ int gv100_nvlink_discover_ioctrl(struct gk20a *g)
2126 nvgpu_err(g, "failed to allocate memory for nvlink io table"); 2127 nvgpu_err(g, "failed to allocate memory for nvlink io table");
2127 return -ENOMEM; 2128 return -ENOMEM;
2128 } 2129 }
2129
2130 for (i = 0; i < top_device_info__size_1_v(); i++) { 2130 for (i = 0; i < top_device_info__size_1_v(); i++) {
2131 table_entry = gk20a_readl(g, top_device_info_r(i)); 2131 table_entry = gk20a_readl(g, top_device_info_r(i));
2132 nvgpu_log(g, gpu_dbg_nvlink, "Table entry: 0x%x", table_entry);
2132 2133
2133 devinfo_type = top_device_info_entry_v(table_entry); 2134 devinfo_type = top_device_info_entry_v(table_entry);
2134 2135 if (devinfo_type == top_device_info_entry_not_valid_v()) {
2135 if (devinfo_type == top_device_info_entry_not_valid_v()) 2136 nvgpu_log(g, gpu_dbg_nvlink, "Invalid entry");
2136 continue; 2137 continue;
2138 }
2137 2139
2138 if (devinfo_type == top_device_info_entry_engine_type_v()) { 2140 if (devinfo_type == top_device_info_entry_engine_type_v()) {
2139 if (top_device_info_type_enum_v(table_entry) == 2141 entry_engine = table_entry;
2140 top_device_info_type_enum_ioctrl_v()) 2142 } else if (devinfo_type == top_device_info_entry_data_v()) {
2141 is_ioctrl = true; 2143 entry_data = table_entry;
2142 else { 2144 } else if (devinfo_type == top_device_info_entry_enum_v()) {
2143 is_ioctrl = false; 2145 entry_enum = table_entry;
2144 continue;
2145 }
2146
2147 if (top_device_info_chain_v(table_entry) !=
2148 top_device_info_chain_enable_v())
2149 break;
2150
2151 is_chain = true;
2152 ioctrl_table[io_num_entries].valid = true;
2153 continue;
2154 } 2146 }
2155 2147
2156 if (devinfo_type == top_device_info_entry_data_v()) { 2148 if (top_device_info_chain_v(table_entry) ==
2157 if (is_ioctrl && is_chain) { 2149 top_device_info_chain_enable_v()) {
2158
2159 ioctrl_table[io_num_entries].pri_base_addr =
2160 top_device_info_data_pri_base_v(table_entry) <<
2161 top_device_info_data_pri_base_align_v();
2162
2163 if (top_device_info_chain_v(table_entry) !=
2164 top_device_info_chain_enable_v()) {
2165 is_chain = false;
2166 io_num_entries++;
2167 }
2168 }
2169 continue; 2150 continue;
2170 } 2151 }
2171 2152
2172 if (devinfo_type == top_device_info_entry_enum_v()) { 2153 if (top_device_info_type_enum_v(entry_engine) ==
2173 if (is_ioctrl && is_chain) { 2154 top_device_info_type_enum_ioctrl_v()) {
2174 2155 nvgpu_log(g, gpu_dbg_nvlink, "IOCTRL entries");
2175 ioctrl_table[io_num_entries].intr_enum = 2156 nvgpu_log(g, gpu_dbg_nvlink,
2176 top_device_info_intr_v(table_entry); 2157 " enum: 0x%x, engine = 0x%x, data = 0x%x",
2177 ioctrl_table[io_num_entries].reset_enum = 2158 entry_enum, entry_engine, entry_data);
2178 top_device_info_reset_v(table_entry); 2159 ioctrl_table[io_num_entries].valid = true;
2179 2160 ioctrl_table[io_num_entries].intr_enum =
2180 if (top_device_info_chain_v(table_entry) != 2161 top_device_info_intr_enum_v(entry_enum);
2181 top_device_info_chain_enable_v()) { 2162 ioctrl_table[io_num_entries].reset_enum =
2182 is_chain = false; 2163 top_device_info_reset_enum_v(entry_enum);
2183 io_num_entries++; 2164 ioctrl_table[io_num_entries].pri_base_addr =
2184 } 2165 top_device_info_data_pri_base_v(entry_data) <<
2185 } 2166 top_device_info_data_pri_base_align_v();
2186 continue; 2167 io_num_entries++;
2187 } 2168 }
2188 } 2169 }
2189 2170
@@ -2196,7 +2177,6 @@ int gv100_nvlink_discover_ioctrl(struct gk20a *g)
2196 g->nvlink.ioctrl_table = ioctrl_table; 2177 g->nvlink.ioctrl_table = ioctrl_table;
2197 g->nvlink.io_num_entries = io_num_entries; 2178 g->nvlink.io_num_entries = io_num_entries;
2198 2179
2199
2200 for (i =0; i < io_num_entries; i++) 2180 for (i =0; i < io_num_entries; i++)
2201 nvgpu_log(g, gpu_dbg_nvlink, 2181 nvgpu_log(g, gpu_dbg_nvlink,
2202 "Device %d : Pri Base Addr = 0x%0x Intr = %d Reset = %d", 2182 "Device %d : Pri Base Addr = 0x%0x Intr = %d Reset = %d",