diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/nvlink_gv100.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/nvlink_gv100.c | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c index 3e1b2cda..7457c181 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c | |||
@@ -1461,7 +1461,8 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) | |||
1461 | u32 i; | 1461 | u32 i; |
1462 | u32 links_off; | 1462 | u32 links_off; |
1463 | struct nvgpu_timeout timeout; | 1463 | struct nvgpu_timeout timeout; |
1464 | u32 pad_ctrl, swap_ctrl; | 1464 | u32 pad_ctrl = 0; |
1465 | u32 swap_ctrl = 0; | ||
1465 | u32 pll_id; | 1466 | u32 pll_id; |
1466 | 1467 | ||
1467 | reg = gk20a_readl(g, trim_sys_nvlink_uphy_cfg_r()); | 1468 | reg = gk20a_readl(g, trim_sys_nvlink_uphy_cfg_r()); |
@@ -1469,10 +1470,12 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) | |||
1469 | trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(1)); | 1470 | trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(1)); |
1470 | gk20a_writel(g, trim_sys_nvlink_uphy_cfg_r(), reg); | 1471 | gk20a_writel(g, trim_sys_nvlink_uphy_cfg_r(), reg); |
1471 | 1472 | ||
1472 | reg = gk20a_readl(g, top_nvhsclk_ctrl_r()); | 1473 | if (g->ops.top.get_nvhsclk_ctrl_e_clk_nvl) { |
1473 | 1474 | pad_ctrl = g->ops.top.get_nvhsclk_ctrl_e_clk_nvl(g); | |
1474 | pad_ctrl = top_nvhsclk_ctrl_e_clk_nvl_v(reg); | 1475 | } |
1475 | swap_ctrl = top_nvhsclk_ctrl_swap_clk_nvl_v(reg); | 1476 | if (g->ops.top.get_nvhsclk_ctrl_swap_clk_nvl) { |
1477 | swap_ctrl = g->ops.top.get_nvhsclk_ctrl_swap_clk_nvl(g); | ||
1478 | } | ||
1476 | 1479 | ||
1477 | for_each_set_bit(i, &link_mask, 32) { | 1480 | for_each_set_bit(i, &link_mask, 32) { |
1478 | /* There are 3 PLLs for 6 links. We have 3 bits for each PLL. | 1481 | /* There are 3 PLLs for 6 links. We have 3 bits for each PLL. |
@@ -1483,12 +1486,12 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) | |||
1483 | swap_ctrl |= BIT(pll_id); | 1486 | swap_ctrl |= BIT(pll_id); |
1484 | } | 1487 | } |
1485 | 1488 | ||
1486 | reg = set_field(reg, top_nvhsclk_ctrl_e_clk_nvl_m(), | 1489 | if (g->ops.top.set_nvhsclk_ctrl_e_clk_nvl) { |
1487 | top_nvhsclk_ctrl_e_clk_nvl_f(pad_ctrl)); | 1490 | g->ops.top.set_nvhsclk_ctrl_e_clk_nvl(g, pad_ctrl); |
1488 | reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_nvl_m(), | 1491 | } |
1489 | top_nvhsclk_ctrl_swap_clk_nvl_f(swap_ctrl)); | 1492 | if (g->ops.top.set_nvhsclk_ctrl_swap_clk_nvl) { |
1490 | 1493 | g->ops.top.set_nvhsclk_ctrl_swap_clk_nvl(g, swap_ctrl); | |
1491 | gk20a_writel(g, top_nvhsclk_ctrl_r(), reg); | 1494 | } |
1492 | 1495 | ||
1493 | for_each_set_bit(i, &link_mask, 32) { | 1496 | for_each_set_bit(i, &link_mask, 32) { |
1494 | reg = gk20a_readl(g, TRIM_SYS_NVLINK_CTRL(i)); | 1497 | reg = gk20a_readl(g, TRIM_SYS_NVLINK_CTRL(i)); |